does BITS field setting in CSR0-3 take effect immediately?

Go To Last Post
16 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

hi,

Just wanna gain several clks of speed in my SPI interface code, so does the BITS field in CSR0-3 take effect immediately or in the next transfer?

Cheng

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

any one knows?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I don't think it's safe to modify the BITS parameter while a transfer is ongoing.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

really? Then I should wait until the current transfer is finished, right?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I'd say so. If a register doesn't explicitly state that its double-buffered with an automagic register load on transfer complete then I'd assume it isn't and manually synchronize the register updates to the transfers.

-S.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ok, thanks

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

then how about the CSAAT bit?

so if I clear this bit during the transfer, will the corespongding CS pin rise when the transfer finish?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

anyone knows?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I would suggest that it will, the bit status probably won't be cached at transfer start.

I'd kinda suggest you try it though, I suspect this isn't the kind of thing that the atmel boys would expect you to do.

-S.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ok, i will try it. thanks

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I have tested the CSAAT bit, and it just doesn't work.

I can't let the CSn pin to keep low between two data transfer.

I have set the CSAAT bit before I start the two transfer, but then checking from Oscilliscope, the CSn still rised between two transfers.

Then I set the CSAAT bit after I start the first transfer, but the result is the same!

why?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Are you using DMA? Have you read the errata list for the SPI peripheral?

I would recommend using GPIO to control you chip selects.

Hans-Christian

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

no, I'm not using DMA. Yes, I have read the errata for SPI. But there have no information about the CSAAT.

And surprisingly, after I updated the framework to 1.2 and avr32studio to 2.0, the CSAAT starts to work, and I'm sure I haven't changed any code.

Now I also found out that if I clear the CSAAT after two transfer finished, then the problem come back again.

	while (1)
	{
		CC2420_wr_register(CC2420, 0x2Au, 0xAAAA);
	}

signed char CC2420_wr_register(CC2420_t CC2420, CC2420_register reg, unsigned short val)
{
	unsigned long tdr_temp;
	
	
	if ((reg < CC2420_MAIN) || (reg > CC2420_RXFIFO) || ((reg > CC2420_RESERVED) && (reg < CC2420_TXFIFO)) || (CC2420.spi_pins.CS > 3))
	{
		return CC2420_INVALID_ARGUMENT;
	}
	
	
	
	tdr_temp = AVR32_SPI_TDR_PCS_MASK & ~(1 << (CC2420.spi_pins.CS + AVR32_SPI_TDR_PCS_OFFSET));
	
	CC2420.spi->tdr = ((unsigned long)reg << AVR32_SPI_TDR_TD_OFFSET) | tdr_temp;
	
	// wait until data is loaded to shift register
	while (!(spi_writeRegisterEmptyCheck(CC2420.spi)));
	
	spi_set_chip_CSAAT(CC2420.spi, CC2420.spi_pins.CS);
	
	// wait until SPI send out previous data
	while (!(spi_writeEndCheck(CC2420.spi)));
	
	// set to 16 bits format
	spi_set_chip_16bits(CC2420.spi, CC2420.spi_pins.CS);
	
	CC2420.spi->tdr = ((unsigned long)val << AVR32_SPI_TDR_TD_OFFSET) | tdr_temp | AVR32_SPI_TDR_LASTXFER_MASK;
	
	
	
	// wait until SPI send out previous data
	while (!(spi_writeEndCheck(CC2420.spi)));
	
	// here is the trick, if this is not commented, then CSn pin wouldn't keep low
//	spi_clr_chip_CSAAT(CC2420.spi, CC2420.spi_pins.CS);
	
	// set back to 8 bits format
	spi_set_chip_8bits(CC2420.spi, CC2420.spi_pins.CS);
	
	return CC2420_SUCCESS;
}
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I don't understand the Figure 21-6. Master Mode Flow Diagram S in the datasheet.

it didn't mention the LASTXFER bit setting. if I have set the LASTXFER bit in the last transfer, will the CSAAT be automatically cleared after this transfer finished?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

i just did some more test, and it seems this LASTXFER will indeed rise the CSn pin after the transfer finish.

If I don't add this LASTXFER in the last transfer, then the CSn pin will always be low before a different CSn is selected.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

and I found out that you have to read out RDR value before you change the bits setting, otherwise the RDR reading would be different.