Do interrupts get interrupted?

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Hi,

I was reading a link provided by someone here and it says:

The AVR microcontroller disables interrupts upon entering an ISR and the RETI instruction is required to re-enable them on exiting.

Does this mean that if you have two ISR's and one is running, that it can't be interrupted for the second one?

I guess I figured an interrupt could be interrupted by itself even...

Thanks,

Alan

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The current interrupt is disabled on entering the ISR, other interrupts may still be enabled. See a data sheet for a full explanation.

An interrupt can be interrupted by the same interrupt, but you need to write your code carefully to handle it properly. Avoid doing it, if possible.

Leon Heller G1HSM

Last Edited: Thu. Mar 18, 2010 - 12:47 PM
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This has been explained 100 times before - surprised a search didn't find a prior explanation - maybe it's difficult to pick the right search terms?

Anyway, because bocking interrupts run with I set to 0 what occurs if another interrupt source (which could even be the current ISR source) triggers is that the hardware will simply set the ??IF flag for the interrupt type in one of the modules control registers. When the current interrupt ends and performs the RETI control will unwind to main() where one further opcode will execute then on that next cycle the interrupt detection hardware will spot that the ??IF flag is set and trigger that interrupts vctor mechanism. If more than one ??IF are set then they are handled in vector table order (this is the only form of "priority" the AVR8 offers). The danger is if an interrupt source triggers TWICE or more during the course of another ISR handler. There's only one bit to the ??IF flag bits so the system has no way of knowing that 2+ have occurred when that device's ISR is entered. This is why ISRs should always be as short as possible so that other interrupts (or more of the current one) are not missed.

By the way, what has this got to do with GCC? Unless you can think of something I'll move this to AVR Forum where it belongs.

Cliff

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Hi,

I did try a search, and read through some threads, but didn't find what I was looking for. I guess I was thinking about GCC and interrupts, but you are right, this should be in the AVR forum.

Thanks,

Alan

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Well just to add a bit of GCC specific relevance. Hve a read of the manual:

http://www.nongnu.org/avr-libc/u...

Note the use of the attributes ISR_BLOCK and ISR_NOBLOCK. So you could:

ISR(INT0_vect, ISR_NOBLOCK) {
 // this may be interrupted
}

which allows for interrupt nesting (the title of the thread) but this has to be managed very very carefully. If you have a UART interrupt that happens rarely but want to keep servicing ADC interrupts (say) then you could make the UART ISR non-blocking. HOWEVER if you get a burst of UART activity and the UAR ISR takes a while you might stack up several nested levels of stacked interrupts and in the limit you could bow the stack. So NO_BLOCK can be very dangerous unless you are sure all interrupts that are set to it can be handled before the next one might occur.

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Hi,

Thanks Cliff!!

Alan

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My answer is: It depends on your AVR controller.
= legacy and Mega AVR : See answer above.
= XMega AVR : Yes. There are tree interrupt priority levels. Any higher priority level interrupt will interrupt any ISR of a lower priority.

... the only thing you cannot unscramble is eggs...

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wBoellmann wrote:
My answer is: It depends on your AVR controller.
= legacy and Mega AVR : See answer above.
= XMega AVR : Yes. There are t[h]ree interrupt priority levels. Any higher priority level interrupt will interrupt any ISR of a lower priority.
In addition to the three levels on the Xmega, the lowest priority interrupt can be told to service multiple low-priority pending interrupts in a round-robin fashion or not. At least that's what I've read.

Stu

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