Do I really need to use the /SS pin for SPI between two ATMEGAs?

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Hi,

 

When doing SPI communication between two ATMEGAs, I can configure one to be the master and the other slave.  Do I really need to make use of the /SS pin to select the other ATMEGA as the slave? I can understand if SPI is done to another device, e.g., an SPI sensor or something.  But, between two ATMEGAs, I feel making use of the /SS is such a waste of the pin.

 

Thanks!

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unebonnevie wrote:
I feel making use of the /SS is such a waste of the pin.

Without using the selection process with /SS or equivalent, how are you ever going to re-synchronize your communications if e.g. a clock pulse is lost or there is an "extra" pulse from noise or otherwise?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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As Lee says, how else can you reset their synchronization? I suppose you could have some data protocol where, for example, every Nth byte transferred would always be some kind of "sync byte" then, when it was due, you read something else you'd know the closk needed to resync so you'd just stop and restart the SPIs which should reset their SCK counters. But what a hassle when a pin does the job?

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/SS is an essential bit of SPI comms, it is needed to ensure clock sync!

 

Jim

 

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The answer is MAYBE.

 

Master - Does not NEED to use /SS, its just an IO you can use any pin, or none, and the Master will send what you want. However you can ONLY use /SS as an output in this case.

Slave - Does NEED to use /SS because the SPI in the Slave is disabled if it is HIGH, and the IO it uses are just inputs.

 

So, you could save 1 OUTPUT on your master and not use /SS but you would need to tie /SS low on your Slave.  Having done that, recognise that SS is only used as a synch mechanism.  You need some way to determine the first bit in a stream.  here are some alternate possibilities other then /SS

 

1.  No CLK pulses for x time (say 5ms) = end of frame.  In software when you receive bytes, start a timer.  No characters for X time, reset the SPI, and wait for the next byte. (The time just needs to be longer than your worst case back to back byte time)

2. A pulse on the Data line, WITHOUT a transition on the Clock Line.  So, you just pulse the data line, and if it wasn't clocked in, use it to reset the SPI state.  Without reading the datasheet, I am pretty sure you can check the state of the MOSI input.

 

The timer option to replace /SS is probably the easiest to implement, however there are corner cases you need to consider, like what happens if you receive 3 bits (you won't start the timer, and you will be out of sync). 

Unless you are totally strapped for IO, the extra complexity probably isn't justifiable to save 1 IO on your Master.  When you get to that you probably need a chip with a bigger package. 

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strontiumdog wrote:

The answer is MAYBE.

 

Master - Does not NEED to use /SS, its just an IO you can use any pin, or none, and the Master will send what you want. However you can ONLY use /SS as an output in this case.

Slave - Does NEED to use /SS because the SPI in the Slave is disabled if it is HIGH, and the IO it uses are just inputs.

 

So, you could save 1 OUTPUT on your master and not use /SS but you would need to tie /SS low on your Slave.  Having done that, recognise that SS is only used as a synch mechanism.  You need some way to determine the first bit in a stream.  here are some alternate possibilities other then /SS

 

1.  No CLK pulses for x time (say 5ms) = end of frame.  In software when you receive bytes, start a timer.  No characters for X time, reset the SPI, and wait for the next byte. (The time just needs to be longer than your worst case back to back byte time)

2. A pulse on the Data line, WITHOUT a transition on the Clock Line.  So, you just pulse the data line, and if it wasn't clocked in, use it to reset the SPI state.  Without reading the datasheet, I am pretty sure you can check the state of the MOSI input.

 

The timer option to replace /SS is probably the easiest to implement, however there are corner cases you need to consider, like what happens if you receive 3 bits (you won't start the timer, and you will be out of sync). 

Unless you are totally strapped for IO, the extra complexity probably isn't justifiable to save 1 IO on your Master.  When you get to that you probably need a chip with a bigger package. 

 

Thanks for the detailed answer.  To be clear of my usage, this is a communication between only one master and one slave.  In my use case, this SPI communication between the two ATMEGAs never stops, unless the power is unplugged.  It seems more complexity is involved to save a pin.  I'll stick with using /SS (output for Master and input for SLAVE) and assert a LOW to the SLAVE's /SS.

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unebonnevie wrote:
  I'll stick with using /SS (output for Master and input for SLAVE) and assert a LOW to the SLAVE's /SS.

Note that holding the named pins in a certain state "forever" doesn't help with resynchronization.  [on an AVR8 it would just keep the master in Master mode, and the slave in Slave mode]

 

Why not just take the straight path, and assert select to the slave at the start of each transaction, and de-select when complete?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Wed. Jul 17, 2019 - 01:42 PM