Digital frequency locked loop (DFLL48M) SAMDA1 Target operation Problem.

1 post / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hello All,

 

Does anyone know if the operation of the DFLL48M frequency source in SAMD targets depends on the used evaluation board or MCU ? !, I am facing a very mysterious problem while using the DFLL source ,sometimes it works on evaluation board and other times it doesnot the frequency becomes locked,  using the same configurations .

This the configurations i use, Iam trying to use the OSC8M as a reference source for the DFLL84M oscillator.

What does the frequency locking depend on?  and what sources can be used with the DFLL, I tested it on OSC8M, OSC32K,  and XOSC32K and it works on all of them.

PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
 
SYSCTRL->OSC8M.bit.PRESC = CSTSAMD_u8FLLFREF_OSC8M_PRES;
    SYSCTRL->OSC8M.bit.RUNSTDBY = 0x0;
    /*@Comment: the oscillator is always on, if enabled, while it is disabled in standby mode*/
    SYSCTRL->OSC8M.bit.ONDEMAND = 0;
    /*lint -save -e587 ,to solve PClint: Predicate '==' can be pre-determined and always evaluates to True */
    while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) == 0 )
    {
      /* Wait for oscillator stabilization */
    }
    /*lint -restore */
    GCLK->GENDIV.bit.ID = CSTSAMD_u8MCTRL_FLLREF_GCLK_ID;
    while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
    {
      /* Wait for synchronization */
    }
    GCLK->GENCTRL.bit.ID = CSTSAMD_u8MCTRL_FLLREF_GCLK_ID;
    GCLK->GENCTRL.bit.SRC = GCLK_GENCTRL_SRC_OSC8M_Val;
    GCLK->GENCTRL.bit.OE = 0x1u;                    /* @Comment: Output clock to a pin for tests */
    GCLK->GENCTRL.bit.GENEN =0x1u;
    while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
    {
      /* Wait for synchronization */
    }

#endif /*CSTSAMD_coUSE_FLLREF_FREQ_XOSC32 */
  /*2) @Comment: Put Generic Clock Generator  as source for Generic Clock Multiplexer 0 (DFLL48M reference) */
  /*   Sequence of initialization is important; choose MUX 0 then ID of the ref freq, then enable.   */
  /*@Comment: read wait states is set to 1 for 48MHZ frequency.*/
  NVMCTRL->CTRLB.bit.RWS = 1;
  GCLK->CLKCTRL.bit.ID = 0x0;                       /* @Comment: Generic Clock Multiplexer 0. */
  GCLK->CLKCTRL.bit.GEN = CSTSAMD_u8MCTRL_FLLREF_GCLK_ID;
  GCLK->CLKCTRL.bit.CLKEN =1;
  while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
  {
    /* Wait for synchronization */
  }
  /*@Comment:  Enable the DFLL48M */
  /*@Comment: The oscillator is always on,if enabled. also DFLL should be requested before using it to avoid freezing in the device. */
  SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0 ;              /*@Comment: Remove the OnDemand mode */

  /*lint -save -e587 ,to solve PClint: Predicate '==' can be pre-determined and always evaluates to True */
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
  {
    /* Wait for synchronization */
  }
  /*lint -restore */
  /* @Comment: Closed loop operation */
  SYSCTRL->DFLLMUL.bit.MUL = CSTSAMD_u8MCTRL_MUL;
  /*lint -save -e587 ,to solve PClint: Predicate '==' can be pre-determined and always evaluates to True */
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
  {
    /* Wait for synchronization */
  }
  /*lint -restore */
  /*@Comment: Write full configuration to DFLL control register */
  SYSCTRL->DFLLCTRL.bit.MODE = 0x1u;               /*@Comment: Enable the closed loop mode */
  SYSCTRL->DFLLCTRL.bit.WAITLOCK = 0x1u;
  SYSCTRL->DFLLCTRL.bit.QLDIS = 0x1u;              /*@Comment: Disable Quick lock */

  /*lint -save -e587 ,to solve PClint: Predicate '==' can be pre-determined and always evaluates to True */
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
  {
    /* Wait for synchronization */
  }
  /*lint -restore */
  /*@Comment: Enable the DFLL */
  SYSCTRL->DFLLCTRL.bit.ENABLE =1 ;
  /*lint -save -e587 -e961  ,to solve PClint:  dependence placed on C's operator precedence ==, || */
  /*lint -save -e9050 :dependence placed on C/C++ operator precedence; operators '==' and '||' [MISRA 2012 Rule 12.1,*/
  /*@Comment: the lock bits are set when the closed loop mode is enabled.*/
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
      (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
  {
    /*  Wait for locks flags*/
  }
  /*lint -restore */
  /*lint -restore */
  /*lint -save -e587 ,to solve PClint: Predicate '==' can be pre-determined and always evaluates to True */
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
  {
    /* Wait for synchronization */
  }
  /*lint -restore */

  /* @Comment: Generic clock generator "FLL48_GCLK_ID" is selected as the source of the generic clock by setting the ID.*/
  GCLK->GENDIV.bit.ID = CSTSAMD_u8MCTRL_FLL48_GCLK_ID;
  while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
  {
    /* Wait for synchronization */
  }
  /* @Comment: Generic clock generator is selected as the source of the generic clock*/
  GCLK->GENCTRL.bit.ID = CSTSAMD_u8MCTRL_FLL48_GCLK_ID ;
  GCLK->GENCTRL.bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
  GCLK->GENCTRL.bit.OE = 0x1u;                          /* @Comment: Output clock to a pin for tests */
  GCLK->GENCTRL.bit.IDC =0x1u;
  GCLK->GENCTRL.bit.GENEN = 0x1u;    

 

Last Edited: Sun. Apr 5, 2020 - 02:50 PM