DFLL48M in SAMD20: how it works?

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I configured DFLL48M as usual: XOSC32K enabled and used as the reference for DFLL48M, configured in closed-loop mode with a multiplication factor of 48000000/32768. It works.

 

XOSC32K is configured in External Clock mode, so a 32.768kHz clock signal is applied to XIN32K. I was surprised when I disconnected this clock signal and the MCU goes on without interruption. I monitored GCLK Generator 0 (Main Clock) on a GCLK_IO[0] pin and I always see the clock (16MHz, because I set a division factor 3 for Generator 0).

 

At startup, if the input clock is not applied, the MCU blocks. As soon as I connect the input clock, even for a short period, the MCU starts and never blocks, even if the input clock is disconnected. I think the frequency will shift over time, anyway I can't explain how it can generates a clock, even inaccurate, without a reference

 

How it works?

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when the reference clock is stopped, the DFLL48M will operate as if in open-loop mode.

The quote is from a "Reference Clock Stop Detection" section in the description of the DFLL48M.

/Lars