Detecting end of transmit with xmega DMA

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I need to implement RS485 at 115200 baud, so I'm using the DMAC to send data to eliminate the interrupts. I need to turn off my transmit buffer once the last byte has been shifted out.

The question is, how do I reliably determine that the last byte the DMA has written to the USART has completely been shifted out?

I assume I can clear the TXCIF flag in the DMA complete ISR (as it may well be already set due to non-deterministic DMA timing), and enable the TXCIF interrupt which, when it is actioned, will turn off the buffer. This of course assumes the DMA complete interrupt ISR will be actioned before the last byte is fully shifted out.

Anyone done this?

Thanks,
Mark.

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mapelec wrote:
I assume I can clear the TXCIF flag in the DMA complete ISR ... and enable the TXCIF interrupt which, when it is actioned, will turn off the buffer.

Your question is not so clear for me. If you want to clear TXCIF in DMA interrupt, how TXCIF can generate an interrupt? And what is the meaning of "turn off the buffer"?

Ozhan KD
Knowledge is POWER

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electronic.designer wrote:
mapelec wrote:
I assume I can clear the TXCIF flag in the DMA complete ISR ... and enable the TXCIF interrupt which, when it is actioned, will turn off the buffer.

Your question is not so clear for me. If you want to clear TXCIF in DMA interrupt, how TXCIF can generate an interrupt? And what is the meaning of "turn off the buffer"?

Because the DMA uses the DREIF trigger not TXCIF. This means the last byte is in transmission when the DMA finishes. Assuming the DMA finished interrupt happens before the transmit actually finishes I can clear the TXCIF in the DMA ISR and enable the TXC interrupt, then a TXC interrupt will occur when the transmission finishes.

However, I'm not sure the DMA complete interrupt will actually be actioned before the last byte is fully transmitted, there's only 70us or so for it to happen. This means the TXCIF flag may, or may not, be set when the DMA interrupt is actioned. If it's not set then I can be sure the tranmission has not yet completed, but if it is set it may have been set earlier on in the DMA due to the non-deterministic timing of DMA transfers and is not actually due to the transfer of the last byte.

The only way out of this seems to be to only send N-1 bytes during the DMA, and send the last byte manually.

Mark.

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According to XMEGA A manual and AVR1307, when DMA writes successive bytes to USART buffer, TXCIF is set only after shifting of last byte ( and not for N-1 bytes).

XMEGA A manual:

Quote:
TXCIF is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data in the transmit buffer (DATA).

AVR1307:
Quote:
TXCIF is not set until the USART has completed transmitting all data in the transmit shift register and the transmit buffers are empty.

So I am not sure but you can set USART transmit interrupt enable in entire frame of DMA transfer and the interrupt occurs only at the end of serial transmission. This is because of non-empty transmit buffer during transmission.

Ozhan KD
Knowledge is POWER

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Yes, this is what I thought might happen. In which case you can't be sure when the last byte has been transmitted, especially if the DMA complete ISR is actioned after the last byte has actually completed (you can't tell if the TXCIF flag wasn't set due to a gap in the middle of the transmission.

I suspect the solution is to transfer N-1 bytes in the DMA and set a flag in the DMA complete ISR - the foreground code sees the flag set and then waits for DREIF to go inactive before sending the last Nth byte manually. In that case you can reset the TXCIF flag and enable the TXC interrupt. All a bit messy though.

Edit: Actually you suggested I could enable the TXC interrupt and because the pipeline would remain filled by the DMA. This is the bit I'm not sure about, i.e. whether the CPU can freeze out DMA accesses to SRAM for any significant time, or whether the DMA can get access to SRAM in 'gaps' i.e. cycle steal.