Designing to pass EMI testing requirements.

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I'm splitting this off from Amin's thread where he wishes to generate RF signals because I'm interested in avoiding generating RF signals with the hope of someday obtaining the required FCC id. Perhaps somebody else will find this useful too.

I'm not yet going to try for the Euro standards where you shoot it with a tesla to see if it still works.

[img]http://www.barefootelectronics.c...(1).png[/img]

A general idea seems to be to keep high frequency signals from traveling on long traces. A high frequency current radiates RF energy.

So the general advice is:

1. Keep your oscillator close to the processor so the high frequency lines are short. Very helpful to use the internal osc if you can.

2. Bypass caps as close as you can manage to EACH power supply pin. Newer chips have + and - pins right together to make this easier.

3. Ground plane everywhere you can put it on both sides. If needed, the + can serve as a ground plane.

4. Add a little inductance to the power plane to keep the high frequency noise from getting past the capacitor onto the rest of the board.

5. Add lots of inductance to power cords to keep high frequency noise off the external wires.

6. Add caps to any IO lines going off the board to reduce high frequencies on these lines.

7. 4 layer boards help A LOT.

So here is a bypass cap on a 2 sided board. The bottom is ground plane. I think this is a pretty good design, but could be improved. The features are:

a) The capacitor is close to the part.
b) The capacitor is between the part and the ground plane so the RF current tends to flow through the cap, not to the ground plane.

And improvement would be to move the plus connection to the capacitor instead of the IC pin. Also, I could put a ferrite bead in the path from the capacitor PLUS line to provide some impedance between the capacitor/chip to the rest of the + distribution. How about one in the ground line?

I have an article by Earl McCune, Consultant, and David Wyskiel, Wyskiel Technologies in a PDF, but annoyingly, search engines don't want to give you a link to the pdf so you can reference it. If you copy/paste the whole string of names from Earl to Technologies into google, it comes at the top of the list.

Here is the whole board design for you to ridicule.

I already see that I should move C12 to be next to the supply pin 8 instead of on the other side if the ISP connector.

If you don't know my whole story, keep your mouth shut.

If you know my whole story, you're an accomplice. Keep your mouth shut. 

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I would add that a changing magnetic field induces current in proportion to the area of each conductive loop. Minimize the area, particularly of high impedance loops. In your example above C10 could have some fill inside the traces which would reduce the area.

And of course where signals exit the board keep the return path close and use ribbon cable (or even twisted pair ribbon cable). The usual design alternates ground pins and signal pins so the return is always close.

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Quote:
In your example above C10 could have some fill inside the traces which would reduce the area.

Really? There's not much space under C10. I added a fill there you can see in the gerber here.

Attachment(s): 

If you don't know my whole story, keep your mouth shut.

If you know my whole story, you're an accomplice. Keep your mouth shut. 

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Its less frequency than dV/dt or dI/dt. So, part of this means not using logic that is faster than needed. That is, if you can use 74C instead of 74HC, do it.

One of the things I had problems with, over and over, was radiation from external wiring. Power wires, control wires, serial I/O wires, they are all a possible problem even if their operating frequency is low. What I discovered is that it can come from two sources:

1) Power supply "noise" that is coupled into the line through the pullup FET of the logic device driving the line

2) Coupling between IO lines and noisy lines.

In the second case, it sometimes helps to have ground traces or flood on both sides of lines that go to the outside world. Then, you may need to add ferrite beads and small caps to help; these always need to be close to the point where the line enters or leaves the board. That is because if you have this filter close to an IC, then there is always a run between the filter and the outside into which signals can be coupled. Sometimes, "filtered connectors" will help but they are expensive and are usually only justified if you have a board that you cannot readily upgrade.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Be careful with any high speed signals that are leaving the PCB. For example, I had massive EMC issues due to a full speed USB connection (the PCB was a USB device). They were all fixed by adding a common mode choke to kill off the common mode noise and a small bit of capacitance on each line to ground to kill off some single ended noise.

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mid richt seems to be a sd card/mmc connector...
if it is, you are sure you can still insert the card without hitting other components???

emc is effectively all about keeping the forward and return path as close to each other as possible. as then the generation of radiation is lowest. Make sure your ground is good and try to avoid floating pieces of copper, they will ignore the PCB manufacturer and can also contribute to higher radiation levels.

also there still is some cleaning up to do with regards to tracks that are not routed nice. this also impacts ground on a couple of places.

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Torby wrote:
Really? There's not much space under C10. I added a fill there you can see in the gerber here.

Here is what I meant by fill to minimize a current loop. Probably difficult to do with CAD software but is actually the easiest way to lay tape or cut rubylith.

Also a transverse electric field occurs at each bend in a trace, proportional to the current (it is what causes the current to change direction). Arcs rather than angles will minimize the signal coupling to nearby traces.

In most cases, insignificant but probably still measurable improvements.

Attachment(s): 

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Oh. I see what you mean. Yea, I think my cad is wanting to put thermals in.

The traces that I think would be most problematic are the SPI lines, MOSI and MISO that wander from the lower left of the processor, up to the RF module, over to the flash chip and down to the SD card slot.

As far as off board connections, this one has 2 wires to a 3v battery and 1 audio out signal. The speaker connects to B+ and the spk output. Maybe should add some inductor and/or capacitor to these right by the solder pad. The 40 pins on the bottom go to a (hopefully working) TFT display's flex connector.

Perhaps I should do fills to avoid bends in the traces to the crystal? That's 16MHz. Probably the fastest thing on board.

Thinking maybe instead of using an external crystal to control the processor's clock frequency, I should have used the internal osc for that, and used a 32768KHz crystal to control the RTC for time related things. That way I'd have lower f outside.

Other boards in the project will be blinking leds, driving servos and driving motors. I think all of these are fairly low frequency operations and don't really need fast rise and fall times.

If you don't know my whole story, keep your mouth shut.

If you know my whole story, you're an accomplice. Keep your mouth shut. 

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For what it's worth...

I think you guys may be over-thinking things a bit here. It sounds like Torby's board doesn't have any really high frequency data lines--only SPI.

I designed a board some time ago with an SPI interface to microSD, UART interface to GPS, and USB interface to the outside world. At the time, I had no experience with EMC requirement--only a few basic guidelines:

  • Bypass caps on every power pin.
  • High speed signals routed as directly as possible, in order to minimize the size of the current loop.
  • Four-layer board with two external signal layers and internal VCC/GND layers. This keeps signal layers coupled to a return path, and also allows a more direct path for power.
  • GND fill where possible.

In testing, the device was indistinguishable from background noise when not attached to USB. When it was attached to USB, I ran into one issue which almost broke the threshold, but thankfully did not. I think this signal was caused by the fact that I had no ferrite beads on the USB power lines. This document gives an excellent description of how to avoid this problem:

http://www.ti.com/sc/docs/apps/msp/intrface/usb/emitest.pdf

Hope this helps! Unless there are high speed signals you haven't mentioned, I think you'll find it's not necessary to take more than a few basic precautions.

Michael

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For a well bypassed system, Michael's experience SHOULD be the norm. If you can keep the Vcc "noise" (technically, it is not noise because it is quasi-periodic) low enough and there is no fast logic on the board, it should be OK.

I say "should" because AVR Mega/Tiny chips appear to have I/O rise and fall tines in the 3-5ns range. This is enough to cause problems in the outside world if the repetition rate is high enough. As long as it is infrequent enough, the average radiated energy will be low enough to get through. It IS a problem with high rate activities like reading and writing an external parallel device (especially memory) or a high sample rate parallel ADC. These sorts of things also tax the bypassing on Vcc.

So, for Torby's probable application, this is over-thinking. However, for others who may come along, here, with other hardware, its better to be more complete, IMHO.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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I figure if I follow design practices that make it WAY under the requirements, that I might pass the requirements.

From what I read, the 4 layer board sounds like good advice, but the intuitively obvious plan of putting the ground and supply on the outside and traces on the inside is not good. Put the power planes on the inside and traces on the outside.

And mainly, keep the loops short.

If you don't know my whole story, keep your mouth shut.

If you know my whole story, you're an accomplice. Keep your mouth shut. 

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The engineers at the test lab I worked with suggested to route the power and ground first. They suggested that it essential in keeping the loop area small. The source impedance is higher and the local caps do their job. They also said if ground plane is used, it should not extend past circuitry.

EMC testing is done with cables attached, they become antennas. It is often necessary isolate I/O, by keeping spacing from main circuits. Even when opto couplers are used there is coupling in the dielectric of the devices.

It all starts with a mental vision.

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ka7ehk wrote:
It IS a problem with high rate activities like reading and writing an external parallel device (especially memory) or a high sample rate parallel ADC. These sorts of things also tax the bypassing on Vcc.

I'm curious what additional recommendations you might make in a case like that... Would you install serial resistors on the data lines to control rise/fall times?

Michael

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That situation has always been challenging for me.

I've found that it helps to increase the Vcc bypass cap size, and even to use SMT chips on what would normally not be an SMT board. Bypass both the parallel accessed peripheral chip and the MCU (and any mux logic). Try to minimize the current loop area involving the IC Vcc pin, the IC ground pin, and the bypass cap. In one extreme case, it was a bank of 47 ohm series resistors in the busses between the two devices.; this was really a "Hail Mary" but it worked. I guess it slowed the rise/fall times a bit. In another case, it took a board relayout to reorganize the bus and reduce its length.

Sort of hypothesizing, here... I suspect that what happens is due to the simultaneous action on many port pins that have been loaded with a relatively small capacitance. Each pin generates a spike in the Vcc current to charge that load capacitance. Many pins, all at the same instant, make a bigger spike. And, its harder for the Vcc bypass cap to supply that current without a big voltage change (on Vcc). So, still hypothesis, two things happen. One is that Vcc changes (in the manner of a negative going spike with possible following ringing) That can radiate and it can couple into I/O lines through highside pullup FETs that are on. The other is that there is a loop of current formed by the IC and the bypass cap; this can produce a magnetic field that can also radiate. I think. As I said, mostly hypothesis. But, probably not far from "truth".

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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I had a similar situation with a LCD module. The cpu was 3V do I put some lcx series level translators to get 5V levels. In testing, that gave me a large bump at 100MHz. Solution - series resistors cured the problem.

Next problem was a buck converter - that required a layout change and a ferrite bead in series with the diode.

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A few general layout notes accumulated over time.

Treat the xtal path as you would any other differential signal.
Keep both lines parallel and paired for as long as possible.

Watch the ground path between the load caps on your xtal. Keep it short, direct and without interruption.
A guard can also keep in as well as out...

A general rule of thumb to avoid coupling is to set the isolation at 1.5x the trace width.

Ground plane via spacing less than 1/10 of a wavelength of the highest frequency on the board. Typically easy to achieve until into multi GHz radio.

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Torby wrote:
I have an article by Earl McCune, Consultant, and David Wyskiel, Wyskiel Technologies in a PDF, but annoyingly, search engines don't want to give you a link to the pdf so you can reference it.

OT, but if you're using Firefox, I highly recommend the Google/Yandex search link fix extension.

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Anyone have a recommendation for their favourite ferrite bead?

Ross McKenzie ValuSoft Melbourne Australia

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They're all good.

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anders_m wrote:
Torby wrote:
I have an article by Earl McCune, Consultant, and David Wyskiel, Wyskiel Technologies in a PDF, but annoyingly, search engines don't want to give you a link to the pdf so you can reference it.

OT, but if you're using Firefox, I highly recommend the Google/Yandex search link fix extension.

I have opera and chrome. I like opera 'cause it's response is (usually) fast. Unfortunately, a few things don't work with opera, like attaching something to an email using my webmail service. Of course, attaching anywhere else, like here, seems to work fine.

If you don't know my whole story, keep your mouth shut.

If you know my whole story, you're an accomplice. Keep your mouth shut. 

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Kartman wrote:
They're all good.
OK... so out of all the good ones, which do you, or have you, used in the past on AVR designs? (pulling teeth :lol:)

Ross McKenzie ValuSoft Melbourne Australia

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Just like "oils aint oils" so ferites aint ferites.

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So no one can quote a ferrite bead part number that they have used?

Ross McKenzie ValuSoft Melbourne Australia

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valusoft wrote:
So no one can quote a ferrite bead part number that they have used?

I've been using this guy for USB VBUS and GND:

http://www.digikey.ca/product-detail/en/MMZ1005S121C/445-2160-1-ND/765083

But I haven't gone through EMC testing yet with it, so would have a hard time saying how effective it is.

Michael

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Thanks Michael. I had a look at Digikey last night, but there were 4000+ choices, so I thought that I would do a "newbie" and ask first :lol:

Cheers,

Ross

Ross McKenzie ValuSoft Melbourne Australia

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Sorry Ross, I thought you were being funny. Of course, so many to choose from - from the tubes you put on cables, to high current, low current power and signal. Our friends at Wurth have a good range and a nice book that explains the ins and outs of emc.
The basis of operation is that the ferrite is lossy at high frequency, so the high frequencies get 'soaked' up in the ferrite.

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There are various grades of ferrite. All frequency dependent.

Select material first to suit requirement then select physical appearance to suit application.
To mind come F14 grade ferrite used in MATV /CATV broadband amplifier powersupply and transistor biasing.

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Ross,

Have a look at Neosid web site

http://www.neosid.com.au/beads.html

Note a variety of grades. Best option is to get Neosid to advise on grade for Your application.

EDIT: material specs

http://www.neosid.com.au/matnick...
http://www.neosid.com.au/matmag....

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Thanks guys.

Cheers,

Ross

Ross McKenzie ValuSoft Melbourne Australia

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That website would have to be the crappiest ones i've seen in a while. They need to use a content management system like joomla.

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All this talk about big ferrites makes me wonder, is a small ferrite like the one I'm using on my USB jack going to do much good from an EMC standpoint? Would it be best to contact the manufacturer, as ignoramus suggested, or are there other guidelines that can be used for chip ferrites?

Michael

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Michael
have a look a the two bottom links on previous post.
They contain grade versus frequency.

Ferrite beads work by inserting an impedance into the wire threaded through them.