design hint for signal multiplexer

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I am looking for some advice for design hints to make a "signal multiplexer" with an Atmega168.
Signal input comes from 8 digital IO, and output signal goes to one pin. Signal input min period between two front is 800 usec, and same for signal output.
What method would you advice to do this.

I tried:
- output signal handled by timer 1
- input signal read by polling, and using counter1

and:

- ouptput signal handled by polling based on counter1
- input signals polled using counter1

and all written in C.
I got fairly poor accuracy of the output signal as shown by the oscilloscope. I wanted a 1 microsecond accuracy, but it looks signal varies to much.
Any advice ?
thanks

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Use PCINT (Pin Change Interrupt) instead of polling/timing.

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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Thanks MBedder,
Problem with interruptions is to handle 2(or more) interruptions which are very close each other, to avoid any loss of IO pin status change. Any example would help.

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Please specify in more detail what exactly are you trying to get at the output.

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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Likewise, I am confused about what you are trying to do.

Are you measuring amplitude or time interval? What events denote the edges of the time interval, if that is what you are doing? What is the problem with the multiplexer you are now using?

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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To clarify,
On input pins, I have level high between 0.8 msec and 2.2 msec, then low for some 10msec or more, and then again.
On the output, i need to generate a signal which is a "concatenate" and reflect each of the 8 input pins. high between 0.8 and 2.2, then low, then high again for pin 2 , etc... The separator between a group of 8 pins is "low" during more than 5msec.

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So, why not, in a fast loop, just make the output bit the 'OR' of the 8 input bits?

If your clock is, say, 8MHz, you should be able to do such a loop in a few microseconds, maximum. that would be under 0.1% of the nominal pulse width.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Why use a micro at all?
Why not just use a few low level OR gates?

JC

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Quote:

Why not just use a few low level OR gates?


That would assume all the signals are "out of phase" and non-overlapping. That might indeed be the case if the origin of the signals is a "soft multi-channel hobby servo driver" as is often discussed here, but if these are independent then there might be overlap.

And if there is a lot of overlap, then there could be a few microseconds of jitter on the channels.

What needs to be decided here is the precision and accuracy needed. The signals are slow so a few microseconds shouldn't matter.

So you make an output "driver" using compare match with timer1, and have timer1 free-run. You have an output array of how many timer1 counts each channel should be high. Then you march through that array and set the OCR register accordingly, and then do it again for the next one. The dead time and the inter-cycle gap are left as exercises for the student.

On the input side either a very fast poll (if debouncing needed) or interrupt pins can be used. When a transition is seen the TCNT1 is trapped and stored as the beginning or ending count. When the ending count is seen, the subtraction is made and the array entry for that channel is updated.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I guess I don't quite understand the goal.
A timing diagram of the 8 inputs, in their various permutations, and the desired output signal would clarify a lot.

JC

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A agree. A simple 8-in OR gate would seem to provide all the function needed.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Quote:

A agree. A simple 8-in OR gate would seem to provide all the function needed.


I disagree, for the reasons above.
Quote:

That would assume all the signals are "out of phase" and non-overlapping. That might indeed be the case if the origin of the signals is a "soft multi-channel hobby servo driver" as is often discussed here, but if these are independent then there might be overlap.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I assume that the OP wants to demultiplex the signal at the other end of the wire, whatever and whereever that may be. What he is describing is essentially time multiplexing of signals.

The solution here may be to use an SPI interface as a hardware serializer. You can run the clock rate on that pretty high (system clock divided by 2 is the max, I believe) and then you have cut your compute load by a factor of 8. Actually, a little higher, since you will need to signal the receiver somehow about beginning/end of the time slot. So, either toggle or cycle the /SS signal to indicate the end of one frame and the beginning of the next.

It's just an idea.

Stu

Engineering seems to boil down to: Cheap. Fast. Good. Choose two. Sometimes choose only one.

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yes theush, signal inputs may be overlapping. Output is a PPM frame as used in hobby radio control transmitter.

Currently, I have implemented interruption for Input pins (pcint) and polling to build the PPM trame. This is no accurate as I want, oscilloscope shows some light shift in some front of the output signal.

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Quote:

This is no accurate as I want, oscilloscope shows some light shift in some front of the output signal.

Sigh. Didn't I first say:
Quote:

What needs to be decided here is the precision and accuracy needed.

So give some numbers.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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one microsecond is fine, less than 2 or 3usec should be ok.

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Quote:

one microsecond is fine, less than 2 or 3usec should be ok.

Lessee-- 2us allowance on a 2ms pulse width-- 0.15 tolerance, and 8 channels. That will be quite difficult if not impossible with the microcontroller model chosen. Lessee--timer1 has to span 2ms so that's 30ns/tick; /1 at 20MHz is 50ns.

An interrupt-driven approach would "work" but introduce too much jitter when there is any interrupt latency due to another event. And on that model you would have to scramble to get eight edge-interrupt sources unless you use a bank of pin-change. That would be OK, I guess, but you still have a jitter problem if the output ISR overlaps the input event.

The above is really a shame as there are so few events to handle overall--like a couple each millisecond.

A tight loop with a port read and TCNT1 read and then make your own "pin change" masking might work OK. Yep, I think that would work. You'd only get jitter when multiple input pins change during the same "read"--unlikely.

Now, if you want to do it "right"--use an Xmega. Even the A4 has plenty of input-capture channels, and timer(s) left over for the output. Given the slow pulse speeds there should never be any races. Yep, a perfect example of the Xmega being able to do the job that classic AVR8 finds difficult/impossible.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Are the input signals the same standard single channel servo pulses, or somewhat else?

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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As others have suggested, use an OR gate to recreate the multiplexed sequence of PWM pulses (that you should be measuring instead of the demultiplexed channel outputs, if there's any way to access it).

Feed the multiplexed pulse train into the Input Capture input of an AVR.

In the interrupt service routine for the input capture event, compute the length of the preceding state of the multiplexed input signal by subtracting the timer snapshot value cached on the previous activation of the ISR from the newly captured time (which should then be written over the top of the "previous timer snapshot" cache, natch). Then flip the input capture setup to trigger on the opposite edge. Then branch to either a "handle leading edge" or "handle trailing edge" section of the ISR as appropriate.

For leading edges, just check to see whether the previous "idle state" of the multiplexed signal was significantly longer than the usual inter-frame pulse spacing; if so, reset your "which channel is this" counter to "Channel zero".

For trailing edges, store the pulse length in the appropriate slot of your array of received pulsewidths, according to the "which channel is this" counter (which you then increment, of course).

Apologies in advance if I've completely misunderstood the problem discussion

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Quote:

As others have suggested, use an OR gate to recreate the multiplexed sequence of PWM pulses ...

That will ONLY work if they indeed come from the same multiplexed source. It has been asked and answered several times that this is not so; there are multiple sources and thus arbitrary overlaps can occur.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.