Delay line IC - digital

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I am looking for delay line IC for digital signal.
I have some signal which I want to delay in us range (0-999us) with 1 us increment

1. I have looked at DS1100-500, that is good but its only for 500ns.
I can cascade some IC in series to generate delay in us but not for large signal.

2. For us range I have checked LTC6994-2. It is good IC. Only problem is if I try to delay both edges, the input pulse width can never be less than tDELAY, otherwise no output signal is generated.
Tdelay is time set for generating delay.
e.g if set 20us delay, & I send a 1us input pulse, then IC removes it & generate no output instaed of delaying.

3. On net I have checked many IC all have delay of picosecond or nanosecond. 

4. I want IC to be discrete or programmable by discrete components like LTC6994-2 set delay by selecting resistor value.

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How about a 74123 monostable?

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LOL--for those discrete times, one could use -- wait for it -- an AVR. ;)

 

Microsecond resolution could certainly be obtained.  The tricky part might be high-frequency signals.  I guess I might be tempted to use 16-bit timer and compare match to drive the output signal, and an external interrupt of some sort to recognize the input signal.

 

LOL again -- too many projects; too little time.  A single ADC channel with a pot to set delay time, free-running.  As the ADC counts are 0-1023 that is almost exactly the 1us-per-count in OP's spec.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Tue. Apr 14, 2015 - 09:16 PM
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Brute force method--pick an AVR model with 1kB or more of free SRAM.  Circular buffer with up to ~1000 samples.  Each microsecond, sample an input port and log into the circular buffer.  Then take the recorded sample from n microseconds ago, and apply it to the output port.  Gotta cycle count; might need to be in ASM to dedicate two pointer registers.

 

IN  1 (cycle)

STS Z+ 2

 

LDS Y+ 2

OUT 1

 

So 6 cycles for the basic operation.  But Z and Y need to be wrapped, and if the pot is used as mentioned then the ADCH/ADCL need to be read into the "wrap" register values.  Can that be done in 14 cycles (to get done in 20cycles at 20MHz)?  Pretty close.

 

Now, let's take an Xmega with port I/O and DMA...I'm not an Xmega expert and thus haven't exercised the DMA features.  But this should be right up its alley, right? 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I like the AVR approach, but one needs a spec on the minimum pulse width to decide if the uC can do this or not.

 

Xmega DMA is an interesting thought, but at the moment I don't think it would work.

Recall that it is a pseudo-DMA, it runs instead of the uC processor, not simultaneously with it.

 

If this is not for a commercial device, then also recall that the Xmega can easily be overclocked to 48 MHz for simple I/O operations like this,

(Not EEPROM operations, and +/- on which Analog functions can be over clock).

 

JC

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Xmega DMA is an interesting thought, but at the moment I don't think it would work.

Recall that it is a pseudo-DMA, it runs instead of the uC processor, not simultaneously with it.

I'm a novice Xmega person.  But as I recall, DMA can sample a port at defined intervals (a 1us "event"?), and can also drive a port at a defined interval.  And the DMA is double-buffered, so you "pass" a completed buffer from the innie and take it as the next buffer on the outie.  

 

Now, the innie and outie indices need to be offset by the delay time.  Thinking about it, this might be most easily be done by having the DMA buffer length be the delay time, or maybe delay time /2 ?  So you change the delay time by adjusting the DMA buffer length.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Thu. Apr 16, 2015 - 02:11 PM
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I think this is an interesting question, but I'll have to put it on the back burner, as too many higher priorities right now to test it.

 

That said, I was thinking for a generic delay line one needs to be able to continuously read the input, buffer the signal, and read it out, also continuously.

 

I was having a hard time getting my head around the continuous input and simultaneous continuous output with the Xmega's DMA.

 

But, before spending much time on it, I still think one has to know the minimum pulse width of the input signal, and the minimum delay between pulses, and the accuracy of the output timing.

This lets one decide how fast the input signal must be sampled, which lets one know if it is in the realm of possibilities for the Xmega.

One then has to consider the length of the delay, at the given sampling frequency, to decide how large the buffer array has to be.

 

If all of that will "work", then I'd investigate options for making it work.

Without using DMA, as a first stab at this, one might use one ISR for reading the output of a circular buffer.

Another T/C increments the pointer to the input of the buffer.

Then an Analog Comparator ISR stuffs the buffer with ones, or a pin change ISR determines whether to stuff the buffer with a 1 or 0.

 

JC