debugWire and 2 ATMEGA with common RESET

Go To Last Post
4 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi,
From the appnotes I see that debugWire needs no pull-up or RESET pull-up not stronger than 10KOHM.

I have 2 atmegas (88 and 128) connected and normally exchanging data via SPI etc so in order to sync the start-up I always used common RESET line.

At the present state I have also 4053 buffers shielding 2 separate ISP connectors from SPI lines: one ISP is for 88, another for 128 (of course 128 uses USART TX/RX pins for ISP). So the buses are 'shielded' from the programmers in normal operation, as long as RESET is low - as the RESET activates 4053 MUXes. Apparently this is not the best strategy when I start using debugWire?

I also have 5.6V Zener on RESET line.
I have removed capacitor from RESET line.
I want to disable debugWire on 88 (well it already is) and enable on ATMEGA128.
Will be using SPI and AVRISP MKII for programming as usually.

Now the question is, will this shared reset work with debugWire.
The appnote says 'no other devices should be connected etc'. I have disconnected the RESET from another WP pins of the local eeproms and sensors, but due to boards space problems, I wonder if I have to make disconnectable RESET line between the 2 processors via a jumper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The entire debugWire protocol is a bi-directional "1 wire" protocol using nothing more than the _reset line. If two devices hear the commands and respond I doubt anything intelligible will happen!

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

clawson wrote:
The entire debugWire protocol is a bi-directional "1 wire" protocol using nothing more than the _reset line. If two devices hear the commands and respond I doubt anything intelligible will happen!
Smoke signals.

Iluvatar is the better part of Valar.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Please be serious. If I disable debugWire on ATMEGA88 and enable on ATMEGA128 (I said I want to debug AT128, only), there is only ONE output pin. The question is if the logic in AT88 will somehow disrupt the output from AT128 to make it unusable.

The same question if in put pin from 4053 mux can drain enough current to disrupt debugWire comms.