DDS focused AVR

Go To Last Post
6 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

When you program a software DDS higher than 8-bit and lower than 16-bit, overhead starts to increase by a few times (because you need to shift upper bits from the phase accumulator toward lsb (phase address)
The common thing is extracting the phase bits from the phase accumulator (the upper bits, 10-12bits), but you need these bits toward lsb, and shifting cost a lot of instructions. The problem with a DDS is the sample rate, the higher the sample rate the less instructions can be executed in that short time (e.g @ 20MIPS 640 clocks per 32 usec)
Shifting nibbles would be an advantage (in a single clock; two swaps, one buffer, two bitmasks, one merge) e.g shifting upper 10-bits or 12-bits (from a phase accumulator) towards lsb.(to have a phase address pointer)

RES

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Not sure of the point you are making. Are you saying Atmel should design new opcodes into a future AVR to aid this implementation? I thought you normally picked a phase accumulator where sizes were a multiple of 8 bits so it's just a matter of picking out the right byte without shifting?

With so many far faster small micros (Cortex) available I doubt Atmel would see the commercial merit in redesigning a CPU just for this (unless a customer placed a 10m+ order or something ;-)).

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Jesper's MiniDDS does it as fast as it can from ROM. It does not shift at all, it just stores the phase accumulator in one of the index registers in such way that it can directly address with index. Limitation of 256 entry table of bytes though.

And if you put the waveform table into RAM, I think you can make the loop one cycle faster so that you don't use LPM in there.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

it would be stupid to run a SW DDS on other than 8,16,24,32.... bit.
if you want 12 bit, just ADD a 16 times bigger number on a 16 bit DDS.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Quote:

With so many far faster small micros (Cortex) available I doubt Atmel would see the commercial merit in redesigning a CPU just for this

Didn't Atmel already do this with the Xmega? For a given set of DDS parameters, can't a table (or two) be made in SRAM of the desired values, and then DMA be used to send these values to DAC or port(s) or whatever every "trip" of some timing mechanism?

[That said, I wondered why the Xmega didn't have at least a rudimentary MAC Multiply And Accumulate or even provisions for e.g. 16x16 MUL]

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Quote:

[That said, I wondered why the Xmega didn't have at least a rudimentary MAC Multiply And Accumulate or even provisions for e.g. 16x16 MUL]

Because they (Atmel) have the AVR32