Cortex-M7 DWT cycle-counter not running ???

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Can't get the Cortex-M7 DWT cycle-counter to run on the SAME70 Xplained board.
(DWT is Data Watchpoint and Trace).

The set up sequence is as follows:

   /* Enable CPU Cycle counting */
   /* Global Enable for DWT */
   CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
   /* Reset the counter */
   DWT->CYCCNT = 0;  
   /* Enable cycle counter */
   DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;

From this point on, the DWT->CYCCNT register should
be counting.  Looking at register DWT->CTRL, it looks
like the enable did not take.  It's behaving as if
the DWT block is not clocked.  Reg DWT->CTRL remains
at its 'reset' value of 0x40000000.  Expecting 0x40000001.

(fyi DWT_CTRL_CYCCNTENA_Msk has the value 1 (i.e. bit 0))

Q: What is the complete sequence to enable the SAME70 Cortex-M7
DWT block for the part?
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The code from the SAMS/V/E library seems to work.

 

\examples\Atmel\SAME70_Xplained\utils\utility.h

#define RESET_CYCLE_COUNTER()  do { \
        CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; \
        __DSB(); DWT->LAR = 0xC5ACCE55; __DSB(); \
        DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk; \
        DWT->CYCCNT = 0; \
        DWT->CTRL = DWT_CTRL_CYCCNTENA_Msk; \
    }while(0)

#define GET_CYCLE_COUNTER(x)                x=DWT->CYCCNT;   

 

An example showing the use of the macros is \examples\Atmel\SAME70_Xplained\examples\tcm\main.c

 

However, the ISR overhead counter and cycles per instruction counter remain zero for me.  The DWT->CTRL indicates the counters are implemented so I'm not sure why they don't increment yet.

 

DWT->CPICNT;		// counts cycles per instruction
DWT->EXCCNT;		// counts cycles during ISR entry and return

 

Last Edited: Tue. May 17, 2016 - 01:55 AM