Configuring ADC frequency of SAMV71 to 100Khz and 10 Khz

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Hello,

I am new to SAMV71 xplained ultra kit. I want to set the ADC frequency to 100 Khz and another time at 10 Khz. How do I do this?

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As I read the datasheet of SAMV71 I understood that I need to change the prescaler value to change the AFEC ADC frequency. But I could not find much code/documentation/examples to set the ADC frequency in SAMV71 vi athe ASF route. Can someone guide me in this. Only few lines of code about this frequency setting will help my project get going.

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There is this code in afec.c which mentions about prescaler

static void afec_set_config(Afec *const afec, struct afec_config *config)
{
	uint32_t reg = 0;

	reg = (config->useq ? AFEC_MR_USEQ_REG_ORDER : 0) |
		#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
			AFEC_MR_PRESCAL((config->mck / config->afec_clock )- 1) |
			AFEC_MR_ONE |
			//AFEC_MR_PRESCAL(100)
		#else
			(config->anach ? AFEC_MR_ANACH_ALLOWED : 0) |
			AFEC_MR_PRESCAL(config->mck / (2 * config->afec_clock) - 1) |
			(config->settling_time) |		
		#endif
			AFEC_MR_TRACKTIM(config->tracktim) |
			AFEC_MR_TRANSFER(config->transfer) |
			(config->startup_time);

	afec->AFEC_MR = reg;

	afec->AFEC_EMR = (config->tag ? AFEC_EMR_TAG : 0) |
			(config->resolution) |
			(config->stm ? AFEC_EMR_STM : 0);
  #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
	afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl) | AFEC_ACR_PGA0EN | AFEC_ACR_PGA1EN;
  #else
    afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl);
  #endif
}

How do I use this to set the prescaler value?

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More specifically I have a sensor connected to one of ADC ports of SAMV71.I want the sensor analog data to come at 100Kilosamples/sec. How do I do this. I moved from Teensy to SAMV71 hoping that the higher specs of SAMV71 will make my application run faster but the ADC sampling speed is not fast enough.How do I configure it to 100 KS/s or even 10Ks/s. I changed the AFE clock frequenncy in afec.c but this did not improve the ADC frequency.

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I changed the AFE clock frequenncy in afec.c but this did not improve the ADC frequency.

What did you change actually, the afec_clock? That change would only allow a conversion to finish sooner or later, you must still trigger the conversion at a suitable rate (using a timer for example). Or you could have it free running, the sample frequency will then be afec_clock / 21 according to the datasheet  (with afec_clock < 30 MHz).

/Lars

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It is important to distinguish between the ADC clock and the rate at which conversions occur.

 

The conversion rate is usually set by some trigger event, generated by a timer or some other source.

 

The ADC clock controls how long a conversion takes, and must usually be within some fairly narrow range that will allow the ADC to work properly.

 

The ADC clock only controls the conversion rate if the ADC trigger is set to be the end of the ADC conversion. This is the setup for the fastest possible conversion rate. Otherwise, the time between triggers must be longer than a conversion. YOU have to look at the device manual to see how many ADC clocks are needed for one conversion.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Sep 16, 2018 - 03:13 PM