CLK_PER and CLK_RTC on ATtinyxxx

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I'm curious about this statement in the ATtinyx1x documentation:

The peripheral clock (CLK_PER) is required to be at least four times faster than the RTC clock (CLK_RTC) for reading the counter value, regardless of the prescaler setting.

Not that I'd normally do this, but what would happen if I ran both the CPU and the RTC off of OSCULP32K?  Or ran them both off EXTCLK?  I'm guessing the 4x requirement has to do with synchronization, but as I said, I'm just curious about this restriction.

 

Any ideas?

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This reads odd because reading the RTC value wouldn't use CLK_PER, it would use CLK_CPU. The RTC can't be clocked from CLK_PER.

(I'm basing all this on ATtiny1616 but figure it's the same in principle).

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 value wouldn't use CLK_PER, it would use CLK_CPU. 

You really wouldn't know anyhow, what the actual logic processing has going on, it may involve hundreds (or thousands) of gates that is merely described simplistically in the datasheet.  The gate logic/state machine they implemented requires this 4x factor.  There could be state transitions that must sequence through, or avoidance of a race condition, etc.  Maybe they'll give you a schematic of the actual AVR clock section!

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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It's true, I'm only going from the 1616. For that chip there's a nice diagram in the datasheet showing how the clocks are transferred.