Off chip App code

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Question.

When the program code size exceeds the amount of flash in the MCU, it is my understanding that there should be a bootloader on the MCU that will initialize and then copy the app code from flash to RAM.

What happens if the app code is larger than the amount of RAM available? Or does there always need to be enough RAM to hold all of the app code?

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Won't work on AVR but something similar will work on Atmel AVR32, Texas Instruments MSP430, and etc.
TI has a MSP430 loader with an overlay functionality.
Reminds me of DEC PDP-11/34's operating system (we used FORTRAN and overlays).
Could probably use an ELF loader on AVR32 though usually have enough external RAM to hold the entire application.

"Dare to be naïve." - Buckminster Fuller

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Right, I'm not talking necessarily about avr here. I'm mostly wondering about 32-bit MCUs.

Isn't the size of an embedded program limited by both flash and ram size?

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Yes but how its partitioned (internal/external, volatile/non-volatile) can vary.
Hopefully the SAM3S16C (Cortex-M3, 1MB flash) will be out soon.

"Dare to be naïve." - Buckminster Fuller

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In the case of the larger 32bit cpus, the ram is external - eg: the Linux boards I use have 64MB of ram and boot from a serial flash chip. In the case of the smaller 32bit cpus like the LPC1768 I use, you run the code out of flash much like you do with the AVRs. Also, different apps have different requirements for ram - a logic controller probably doesn't need much ram, whereas a datalogger might want quite a bit of it.

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GordonFreeman wrote:
Right, I'm not talking necessarily about avr here. I'm mostly wondering about 32-bit MCUs.

Isn't the size of an embedded program limited by both flash and ram size?

Not necessarily.

If the MCU is capable of executing code from SRAM, you could have a bootloader or OS kernel in flash that is capable of reading files from an external storage like multi-gigabyte SD card. The files could be executable code that are copied from SD card to RAM for execution, one at a time, or swapped in/out whenever needed.

Also if the MCU has an external (code) memory bus, you can connect any kind of external memory you want like flash or ram, and execute code from the external mem.

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Atmel AT91SAM9G45 (and their other ARM9 chips) are interesting in that they have a bootloader mechanism that can read directly from SPI Nand memory. In the old days you had to have at least some NOR flash attached to the external address and data busses of a chip which would be used for a small bootloader that would then have the "smarts" to be able to read Nand itself. It would then load out the main Linux image (possibly decompressing it) from Nand and into DRAM. With these newer chips that have the "smarts" built into the silicon you can save yourself the cost of a NOR.

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It seems to me cpu code is not limited to the size of internal flash. Even on AVRs. I can imagine an interpreted instruction fed to AVR through SD card for example. But that is not the native assembler, isn't it?

Now, AVRs can execute program exceeding their internal flash size. For example you can have a SD card with libraries (functions) and AVR will flash portions of code from external to internal memory on the run. That is not a problem for most AVRs. And of course you are limited to 10000 loads if data is supposed to last for 100 years. But who knows, perhaps it gives 100000000 cycles if you only need to hold this library for 1s? Never tried that but perhaps I will transform one page of flash (for example the last of application section) to such pseudo DDR memory.
Where is my m8...

Quote:

What happens if the app code is larger than the amount of RAM available?

Then you need to use a dynamic memory allocation. A portions of data are loaded and removed on demand. Dynamic memory for data is implemented on AVR libc IIRC (search for malloc).

No RSTDISBL, no fun!

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Quote:

I can imagine an interpreted instruction fed to AVR through SD card for example.

Many prior threads about this. Your suggestion of 10,000 SPMs usually comes out as the "best" solution but also note: http://www.harbaum.org/till/nano... which gives you the possibility of that "interpreted from SD" using a Java VM.

Other suggestions regularly made are a p-code interpreter, Forth (of which there are several), possibly a BASIC intepreter, a CPU "emulator" - one idea would be an AVR simulator running on the AVR but a working practical example is the person who has a Z80 emulator that can really run CP/M on an AVR: https://www.avrfreaks.net/index.p...

(oh and implementing an AVR core on an FPGA so it can make opcode fetches from RAM rather than just flash).

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Impressive projects..

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oh and implementing an AVR core on an FPGA so it can make opcode fetches from RAM rather than just flash

I read on Atmel's site there are AVRs integrated with FPGA and these do execute from SRAM.

AVRs have OCD which can force them to execute any instruction from OCD register (the trick is called a software breakpoint).. Unfortunately the trick is not accessible from application :( And it is proprietary.

No RSTDISBL, no fun!

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Quote:

I read on Atmel's site there are AVRs integrated with FPGA and these do execute from SRAM.

Oh the virtually dead and buried FPSLIC? Well yes I guess there are those but I'm talking about people using the AVR clone from www.opencores.org on a generic FPGA like an Altera or Xilinx.

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I can remember telling an FAE/Sales about some interest in FPSLIC and she told me to forget it, and get it out of my mind. She was right!!

Jim

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