Can't find in datasheet - PWM timer / pin phase relationship

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I am trying to determine if a PWM timer would be in perfect sync with a pin change operation.

I need to set up a timer to change a pin at exactly the same time that an out instruction occurs. It is critical that I change 9 bits at exactly the same time, with no more than a 2 nanosecond margin of error.

I will not be able to experiment on real hardware for a while, so if someone knows where I can find this info, that would be great.

My only other option would be the addition of a pair of 74HC373 latches tied to the clock to latch my 9 bits back into sync, but I would prefer an AVR only solution.

logically, I would assume that everything happens internally on a clock transition inside the XMega, but I have found this not to be true in other respects.

Thanks,
Brad

I Like to Build Stuff : http://www.AtomicZombie.com

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I don't think anybody else would even think of trying that. I don't think anybody else would get it to work. :wink:

The largest known prime number: 282589933-1

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As far as I understand things, the ability to arbitrarily set or clear a pin using the counter/timers has disappeared from the devices with the "advance" to XMeagre, so good luck with that.
Not that there might be some way of achieving your aim though, maybe using DMA or the event system.

John

Four legs good, two legs bad, three legs stable.

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Hmmm--if you pretend that your data is the low 9 bits of an external memory-mapped "peripheral", I wonder if A8 would fire at the same time as A0-A7.

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Nice idea. It probably depends on how flexible the external addressing is. On the non X Megas I have had to "waste" a pin because the address size was not infinitely adjustable. I haven't checked this on the XMeagres.

Four legs good, two legs bad, three legs stable.

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I did a small test with DMA triggered by the PWM CC event to transfer from SRAM to a PORTx.OUT. There seem to be a four cycle delay from change of the PWM pin before the PORTx change.

So I triggered the DMA on another CC-channel on the same timer, set to four less than the PWM and then the changes happens on the same clock tick.

But, there's no guarantee that the DMA controller have access to SRAM exactly on the cycle, so there may be a couple of cycles delay in that case :-(.

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Wow, "cycles" of delay is simply out of the question. I could probably deal with 2ns of delay, but not a full cycle. I too am addressing an external SRAM, but I am doing so at 60MHz from the XMega.

Brad

I Like to Build Stuff : http://www.AtomicZombie.com

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On a side note, anyone know where I can find the firmware for an XMEGA384 DFU bootloader??? I found every doc on the subject, but cannot seem to find the actual firmware so I can get FLIP to talk to the XM384.

brad

I Like to Build Stuff : http://www.AtomicZombie.com

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It looks like you are using one of the larger Xmegas. The smaller E series has some programmable logic gates that can be tied to pin operations. Perhaps a one chip option.

JC