I wanted a longer delay (4 or 8 s) for the Watchdog, using a ISR but with no reset.
The WDTON fuse is cleared on the ATMega328p.
Following the 328p datasheet example (p 53) for altering the prescaler just does not work. I've tried many other combinations without success. The WDP bits remain cleared, and the timeout remains at 16ms.
The commented out line, which includes
was due to the advice on p51 of the datasheet:
The sequence for clearing WDE and
changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and
WDE. A logic one must be written to WDE regardless of the previous value of the WDE
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
However Atmels code example did not explicitly clear WDCE, and it makes no difference anyway. The WDP bits remain cleared, regardless.
sei(); // enable interrupts MCUSR &= ~(1<<WDRF);// Clear WDRF in MCUSR cli(); // disable interrupts wdt_reset(); WDTCSR |= (1<<WDCE) | (1<<WDE); WDTCSR = (1<<WDIE) |(1<<WDE) | (1<<WDP2) | (1<<WDP0); //WDTCSR = (0<<WDCE) | (1<<WDIE) |(1<<WDE) | (1<<WDP2) | (1<<WDP0); sei();