Can someone explain SEEPROM Sectors to me

Go To Last Post
4 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

So I get what SEEPROM is, an EEPROM emulation layer on top of flash memory, but it's the details behind it that really throw me for a loop. I've been at this for more than 1 day now.

 

So you can have up to 64K in virtual EEPROM and it's divided into blocks and pages similar to flash memory. You configure the blocks in a sector and the virtual page sizes.

 

So the whole sector thing is really throwing me for a loop and the data sheet is as usual pretty vague about them.

 * I know a sector contains a given number of blocks

 * I know there are 2 sectors and only one is active, a switch causes the new active to be formatted beforehand

 * I know that there's more pages than can fit into a sector so you have some page overflow outside the sector

 

Here's what I don't get

 * Where are these 2 sectors? The data sheet only says their at the end of the main block. So I'm assuming you take a portion of the end of the main block and then divide it equally in two, and there you get your two sectors?

 * What is the point of sectors? I'm assuming wear leveling?

 * The datasheet mentions multiple sectors also have to do with pages beyond the max page index and that triggers a sector change? I don't understand this at all.

 * Why is there always more pages that can fit into a sector, why is that? I also feel like this has something to do with a sector change.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I suggest you look at datasheets for actual Serial EEPROMS which can explain things better than a datasheet in this case can.  The Microchip datasheets are pretty clear on the things you bring up.

 

junebug12851 wrote:

Here's what I don't get

 * Where are these 2 sectors? The data sheet only says their at the end of the main block. So I'm assuming you take a portion of the end of the main block and then divide it equally in two, and there you get your two sectors?

Yes.

 

 

JIm

 

EDIT:

Here is a brief explanation of the page writing:

https://learn.sparkfun.com/tutor...

 

About half way down the page.

 

Theres other on Google you just have to ask a specific topic  .

 

 

 

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

Last Edited: Fri. Sep 20, 2019 - 07:39 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I think they are talking about the "SmartEEPROM" feature of the SAMD51 (unfortunately abbreviated as SEEPROM, same as "Serial EEPROM")

SmartEEPROM seems to be a scheme for using some of the Flash memory in a way that allows byte-wise writing.  It looks like a sort of virtual memory scheme (like copy-on-write VM pages) on top of the flash NVM.   The documentation is ... clear as mud, and occasionally wrong.  It's not immediately obvious (to me) how much of their fancy algorithm is implemented in the hardware, and how much has to be done in software.

 

  1. The algorithm consists of virtually mapping physical portions of the NVM to logical addresses with an indirection mechanism. A physical page is assigned to a virtual page address and is kept as long as no bit has to be flipped from '0' to '1', as this operation requires a full block erase. In case such a transition is required, a new physical page is assigned to the modified virtual page (placed in the Flash area reserved for the SmartEEPROM). Writing the virtual page affects the cycling endurance of the SmartEEPROM.

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Yes I was talking about SmartEEPROM and yes it's definitely clear as mud lol. I'm more trying to learn the ins and outs of SAMD51 and currently learning the SAMD51 NVMCTRL section of the datasheet and it goes into a small sub-section for SmartEEPROM but I'm just not really getting it because there's so much that is vague or unanswered. I guess I mostly understand it but sectors are a big thing holding me back.

 

Thank you for your input, I'll continue working through the data sheet but I agree it's terribly vague, unclear, and has errors.