Can not get the SPI to communicate over clock/128

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S_K_U_N_X
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Posted by S_K_U_N_X: Mon. May 11, 2020 - 11:24 PM
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I noticed something in some code I wrote the other day and got to wondering.  I have created a master to emulate a play station controller. I'm using a atmega328 with a 12MHz clock. The real playstation sends out a 250kHz-500kHz clock pulse (4us per period) but the best I could do was 93.75khz ? 93 works fine but if I have the room I'd like to use it.

 

  // SPI, master, clock/128 = 93.75khz (187.5 didn't work...)
    SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR1)|(1<<SPR0)|(1<<DORD)|(1<<CPHA)|(1<<CPOL);

 

I'm curious what else I should be looking at. I can see it on my scope and the signal does as I asked it to but the controller does not keep up. I know my clock CP** setting are right. Not that I figure it mattered but clock/64 or c.lock/124 (with double speed) both failed to work.  Maybe I need to look at my byte spacing? If other things could affect this I could get a screen shot of the analyzer. Looks ok to me.

 

 

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AVR Microcontrollers, megaAVR and tinyAVR
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ka7ehk
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Posted by ka7ehk: Mon. May 11, 2020 - 11:34 PM
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You have to get CPOL and CPHA right. Sometimes, it takes some carful checking of the waveforms. Sometimes you have to check when data edges change on MISO to tell what the slave expects on MOSI. 

 

Also, with your scope, check the gap between bytes. Things can fail in odd ways if that is too short.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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S_K_U_N_X
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Posted by S_K_U_N_X: Mon. May 11, 2020 - 11:50 PM
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I tried byte spacing form 100us to 500us.

Here is a blurb about the play station protocol. I'm pretty sure I have that right?

 

The clock is held high until a byte is to be sent. It then drops low (active low) to start 8 cylces during which data is simultaneously sent and received. When the clock edge drops low, the values on the line start to change. When the clock goes from low to high, value are actually read. Bytes are transferred LSB (least significant bit) first, so the bits on the left (earlier in time) are less significant.

 

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ka7ehk
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Posted by ka7ehk: Tue. May 12, 2020 - 12:01 AM
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Which MCU are you using?

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Kartman
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Posted by Kartman: Tue. May 12, 2020 - 12:05 AM
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My strategy would be to get the bit rate correct - try on different hardware if you need to. It could be the slave can hold the clock signal high as a form of handshake - I've not read up on the playstation protocol. Once you've got that working, then you can introduce changes to see where it goes wrong. 

Using the USART will allow you to have finer control over the bit rate.

 

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S_K_U_N_X
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Posted by S_K_U_N_X: Tue. May 12, 2020 - 04:01 PM
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Jim,  an atmega328.

 

Kartman, good point. I do have a mega 32u4 that works at the right speed and also there is one obvious difference. The playstation is  a 3 volt logic where the mega328 is using 5v. The playstation is said to be 5 volt tolerant but the mega 32u4 is using 3.  Maybe it is having a hard time reacting in time. That would explain it no?

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Kartman
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Posted by Kartman: Wed. May 13, 2020 - 12:20 AM
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S_K_U_N_X wrote:
Kartman, good point. I do have a mega 32u4 that works at the right speed and also there is one obvious difference. The playstation is  a 3 volt logic where the mega328 is using 5v. The playstation is said to be 5 volt tolerant but the mega 32u4 is using 3.  Maybe it is having a hard time reacting in time. That would explain it no?

 

I fail to see your correlation between voltage and reaction time.

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S_K_U_N_X
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Posted by S_K_U_N_X: Wed. May 13, 2020 - 06:22 PM
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I once read that the clock signal can have troubles pulling up/down on a 5v vs 3v line. Is that a false claim?

 

If the data coming back is not pulling +/- 5v quick enough could the Master have a hard time reading faster wave forms?

 

 

Attachment(s): 

Image icon PS2USB_5V.png
Last Edited: Wed. May 13, 2020 - 06:25 PM
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ki0bk
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Posted by ki0bk: Wed. May 13, 2020 - 06:25 PM
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The fact you have not connected AVCC/AGND is most likely your problem here, as you have only half of your chip powered up!

Jim

 

 

(Possum Lodge oath) Quando omni flunkus, moritati.

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Kartman
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Posted by Kartman: Wed. May 13, 2020 - 11:51 PM
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S_K_U_N_X wrote:

I once read that the clock signal can have troubles pulling up/down on a 5v vs 3v line. Is that a false claim?

 

If the data coming back is not pulling +/- 5v quick enough could the Master have a hard time reading faster wave forms?

 

There is nowhere near enough information in that statement to determine either way. What clock signal? Why would the master read a waveform? Form a concise question and you'll get a concise answer!

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S_K_U_N_X
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Posted by S_K_U_N_X: Thu. May 14, 2020 - 12:06 AM
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The fact you have not connected AVCC/AGND is most likely your problem here,

 That is not the correct schematic, just showing how the SPI is wired up and what resisters are in place.

 

Kartman, I suppose its not relevant, it was just a thought I had based off your advice. I plan to connect a scope and monitor the voltage on a graph anyways if I see anything that stands out ill comment further with the output.

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S_K_U_N_X
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Posted by S_K_U_N_X: Sat. May 16, 2020 - 05:19 PM
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Here is a scope capture.   The top scan is normal speed and the bottom is where I double it. I should get a 0x9E from the 0x42 command. When I double it I get 0x82 back. This is what I meant above by saying the line is not pulling back up fast enough but that was merely a guess on my part. What could cause the slave not to react in the way it is capable of acting.

Attachment(s): 

Image icon spi.png
Last Edited: Sat. May 16, 2020 - 05:20 PM
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