Can 8Mhz clock run 400khz TWI?

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Hi, new to avr's and im awaiting a atmega168. I need to interface a slave at 400khz. Will I be able to do this without an external clock?

Thanks

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Section 20 of the datasheet expalins how to set the SCL frequency.

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Right, so if i set TWBR to 2 and with no prescaler value I should be fine, right?

((8000000 / 400000) - 16) / 2 = TWBR

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You'd also have to look at the timing diagrams. Using 8MHz clock to get 400KHz is cutting it close. The automotive M168 recommends a TWBR of >10 when using Master mode. I think t_low is violated -- shorter than the spec.

Just checked the datasheet:
Note 7 for the "2-wire Serial Interface Characteristics" section says

Quote:
"The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement
will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega48/88/168 devices connected to the bus may
communicate at full speed (400 kHz) with other ATmega48/88/168 devices, as well as any other device with a proper tLOW
acceptance margin."

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Actually the data sheet formula has a typo, it should be (1/(2 Fscl) - 2/Fck).

At 8MHz clock with 400 KHz 2-wire, I got a 1 microsecond Tlow and the data sheet said 1.3 microseconds is the minimum for the 2-wire standard.

If TWBR is not a problem(?), then another AVR chip will work with the 1 microsecond Tlow. However, a non-AVR part may require the 1.3 microsecond minimum and not work, or it may not care and work. It is strictly up to the other non-AVR 2-wire part and how it reacts.

About the TWBR of >10, ATMEL has known about the formula error for quite some time (it was their own support that gave me the correct formula) and have not updated any data sheets as far as I have seen (even data sheets that have had numerous updates since the error was found). The point is the data sheets are not reliable. You will need to open a support tag with ATMEL if you need to set TWBR below 10 on the ATmega168 in master mode. They are the only ones that can really tell you if the automotive data sheet TWBR note is correct for the non-automotive part also or not.

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I just realized this while taking another look at the new formula.

Using the corrected formula, a Fscl of 400 KHz makes this true: Tlow = 1.25 microseconds – (2/Fck).

Now, what can you subtract from 1.25 microseconds to get 1.3 microseconds :roll:? It appears you need a negative time warp to meet the Tlow specification at 400 KHz Fscl rate, which cannot happen. The formula describes an asymptotic result that can only approach and never quite reach 1.25 microseconds, no matter how fast Fck is. Obviously it can never get to 1.3 microseconds.

A Fscl of about 384.615.KHz gives a 1.3 microsecond value for 1/(2 Fscl). However, the AVR clock speed still subtracts from this value. A 20 MHz AVR clock is .05 microseconds (which becomes .1 microseconds as 2/Fck). So, 1.4 microseconds – .1 microseconds = 1.3 microsecond Tlow. The 1.4 microsecond Fscl makes about 357.142 KHz the best possible Fscl at 20 MHz AVR clock, that still meets the 1.3 microsecond Tlow minimum.

Maybe ATMEL is not keen on correcting the data sheets because this suggests the data sheets should have a disclaimer that 400 KHz 2-wire will only work with devices that tolerate an out of specification Tlow. Could this have anything to do with any of the 2-wire problems many people have experienced in the past?

BTW, because the Fscl values are derived from the TWBR and 2-wire prescaler, the example values shown as maximum Fscl above cannot be exactly reached. They are only theoretical values based on the formula (real/usable values will be lower).

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I see now, so unless my device allows a 1 microsecond low it probably wont work.. so i guess i'll be forced to use an external clock.. but still this is weird because i know people have used an arduino that has an atmega168 and a 16mhz clock to interface over TWI at 400khz..

I guess im just going to have to wait till my chip gets here to try it out..