Bypass Capacitors - Closer to which leg on TTL?

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Ok, so as many people advocate it is a very good idea to use bypass capacitors to reduce voltage droop, noise and ringing in your circuits, and this has been accepted as best practice for a long time indeed. The idea being that you place them as close as possible to the IC's as you can to reduce track or trace inductance and therefore increase their efficiency and effectiveness.

 

When using SMT components many advocate placing the bypass capacitors on the underside of the board so that they can be placed between the legs of the IC's to get them even closer. I am one of the 'old school who use THT for convenience and because of my ageing eyesight and numb fingers.

 

Now, lets take just for he purpose of my question the age-old 74LS00 quad NAND gate. VCC is on pin 14 and GND on pin 7 which I am absolutely sure almost everyone who uses them knows.

 

 

The VCC and GND are as in most 74 series TTL on opposite corners of the IC. Being someone who uses and has used THT all my life, I have always placed bypass capacitors close to the VCC pin at the 'head' of the IC and had a longer but as short as possible GND track or trace to the other side. This is the way I have seen them placed on many boards making extensive use of 74 series TTL.

 

My question that popped into my head while I was prototyping the other day is, given this pin layout, should I be placing the bypass capacitor close to VCC and running a short track or trace to GND, placing it close to GND and running a short track or trace to VCC, or placing it on a long side and running equal length tracks or traces to both VCC and GND? Inquiring minds wonder about such things.

 

I haven't seen any discussion around this particular point that comes to memory, and my Google fu doesn't seem to offer up any wisdom on this either.

Wayne

East London
South Africa

 

  • No, I am not an Electronics Engineer, just a 54 year old hobbyist/enthusiast
  • Yes, I am using Proteus to learn more about circuit design and electronics
  • No, I do not own a licensed copy of Proteus, I am evaluating it legitimately
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What matters is lead inductance (shorter better).  Since you may well have a gnd plane on the bottom, put the cap at VCC , and drop a lead down to the surrounding gnd plane.

In reality, you will prob have not much too trouble unless you are pushing the limit and with no caps for a mile---sometimes none included at all (bad...bad...bad).

A wide track (or plane) has lower inductance.

 

It's QUITE odd you asked this, since less than 12 hours ago I was reading an interesting article about this same question about SMT parts!

https://www.analog.com/en/techni...

 

 

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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How do you run your power traces? 

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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Devices with diagonally-opposite power and ground do represent a big problem. I clearly remember using some DIP  8051s with power and ground on opposite corners and going through some major pain getting caps situated so that the product would pass CE emissions tests. That changed drastically when we went to a different package (TQFP ???) with different power pin locations.

 

For most TTL, I've a.ways assumed that edge rates are slow enough so that EMI is less of an issue. I do not know if that is true. Might not be true with the highest speed versions. It is true with standard CMOS but not true for HC and other highest speed logics. BUT, for reasons outlined in the next paragraph, it tends NOT to be a problem for CE testing. You need to get to the level of thousands of gates before that starts happening, USUALLY.

 

With MCUs and other large scale logic devices, the cause of the problem is pretty subtle. Every inverter (and every BIT of every latch, from the ALU to SRAM has several) drives a bit of capacitance. It takes a pulse of current (from the power supply) every time that inverter output goes high, and there is a discharge pulse every time that output goes low. The amplitude of the pulse depends on the capacitance (typically the number of gate inputs on that line) and the dV/dt for the signal. For an MCU, there are thousands of inverter/gates that change logic state on every clock edge. For common MCUs with rise and fall times of a few nanoseconds, a power input pin can see current spikes exceeding 100mA and with a pulse width around 3ns (with current technologies). To see that, you need a scope with considerably more than 100MHz bandwidth AND really carefully made connections between the circuit and the scope. As a result, most of us will never see the real current spikes but we CAN see the lower frequency impact of those spikes. 

 

Everything I do these days is SMT. I always incorporate a ground plane on the circuit board. And, I use a 10nf or so as close to the power pin as possible and a very close via from the other end of the cap to the ground plane. You are actually better with a 10nF or 100nF , usually, because 1uF or 10uF, even SMT, has more inherent series inductance. That inductance prevents the cap from functioning well at frequencies above 50MHz. You only need to look at the self-resonant frequency of the cap to see what is happening. Lead inductance is why it is so hard to properly bypass packages with power and ground on opposite corners. 

 

Now, lets be careful about this. ANY time you have fast edges driving lots of capacitance, there can be real pain. One such example is driving a MOS power transistor gate. There are other problems driving inductive loads but these tend to be solvable with snubber circuits. EVERY part of the circuit needs to be evaluated, on its own. On the other hand, a 100nF cap on every power supply pin is really cheap insurance.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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WayneZA wrote:
Being someone who uses and has used THT all my life, I have always placed bypass capacitors close to the VCC pin at the 'head' of the IC and had a longer but as short as possible GND track or trace to the other side.
Close enough can be good enough.

Radical Brad Hacks – Vulcan-74 Page 2 | AtomicZombie DIY Plans (AtomicZombie ®)

[near bottom]

All VCC and GND rails tied together.

[last paragraph]

Decoupling capacitors are placed in each corner of all 24 breadboards, the goal being a reduction in high frequency switching noise and quick power spikes. The value of the decoupling capacitors uses is .01uF (microfarads), so the marking on the face will be 104. The large breadboard is now ready for use, with all power and ground rails tied together.

"Dare to be naïve." - Buckminster Fuller

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gchapman wrote:
The value of the decoupling capacitors uses is .01uF (microfarads), so the marking on the face will be 104

Hmmm - Something doesn't match up there. Perhaps a typo and it should have been: The value ... is 0.1uF

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Brad's words are correct.

Bypass Multi-Valued Arrays by Dr. Howard Johnson

...

My advice is this: What's important when combining values is to make sure that we are maintain the same L/C ratio in each new section of the design: smaller C, and smaller L at the same time. 

...

The effect of the array is the same as if I had a single capacitor with 10 uF, and 0.01 nH, values 1000 times less than the those of the bulk capacitor. This balance tends to keep the power-to-ground impedance more or less constant (within a factor of 30 or so) over a very wide frequency range.

Characteristic impedance is proportional to the square root of L/C.

 

"Dare to be naïve." - Buckminster Fuller

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I think I have always seen the caps at the top of the chip - that is, near VCC.  Of course if there's a ground plane that is the obvious choice, but even if not, there will often be another row of chips just above with its own ground trace, and the bypass caps for the lower row can connect to the ground trace for the upper row.

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The value of the decoupling capacitors uses is .01uF (microfarads), so the marking on the face will be 104.

 

I don't think Winterbottom was questioning the stated value, (whether it should be 0.1 uF or 0.01 uF), but the fact that the caption stated 0.01 uF and then wrote that the cap would be marked "104".

 

104 for a small ceramic cap is, I believe, based upon a 10^ x type scaled picofarad scale.

104  refers to a 0.1 uF cap.

 

So yes, I think there is a typo in the comments, as a 0.1 uF cap, (not a 0.01 uF cap), would have a "104" on the chip.

 

JC

 

Last Edited: Fri. Sep 16, 2022 - 07:10 PM
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WayneZA wrote:
I was prototyping

 

Is this 7400 the only one, or there are many /mixed 74'/ onboard?

 

When many, you can simulate 4-layer board by adding Vcc and Gnd tinned buses on component side: they will look as two interlacing combs.

Normally, cap 0.1uF is placed nearby Vcc, which assume the ground plane is all around, while Vcc can be not.

 

 

 

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Thank you to all for your comments. Interesting reading! Interesting links too, thanks for taking the time.

 

Generally peaking I will build a circuit on breadboard(s), then if it works as expected or I want to do more development I transfer it to Veroboard (my preferred more permanent development board), and then I will design and produce a home-made single-sided PCB. sometimes I will leave the circuit on Veroboard if it does not require refinement in the form of a PCB. I use the laser printer toner transfer method, etch with HCL and H2O2 and drill the board myself using a Dremel clone and a small Dremel workstation drill press, so double-sided boards are a bit of a stretch for me.They are possible but not trivial, hence my use of single-sided boards.

 

Obviously when working with breadboards and Veroboard I don't have much flexibility, so I will place the bypass caps close to the VCC pin and then run as short as possible a jumper or link to GND from the other side of the capacitor. On PCB's I usually do a copper pour isolation routing type board, but there obviously limitations being single-sided. I usually join the copper islands together using short jumpers through the board and I use many more than the number required for continuity to try and ensure as good a ground plane as I can.

 

Fortunately I have not (yet) had the need to drive the TTL chips that I use that hard in my designs, but that does not mean I won't get to that point in the future so your solutions and observations are very useful, thanks. TTL are not the only integrated circuits I have encountered this on as I'm sure you guys must know, just the ones that easily spring to mind for the purposes of my questions. To answer the question about how many TTL chips my experiments and prototypes use, it ranges from a single one to many interlinked ones depending on what I am trying to achieve, so basically both sides of the coin.

 

On the idea of using the GND pin of an adjacent TTL chip instead of the GND leg of the chip the bypass capacitor is attached to's VCC pin, does this not defeat the purpose a bit, because the bypass capacitor is no longer at the power pins of each chip but rather sort of stitched across the board between chips Just asking as my limited understanding on the subject is that each chip required its own bypass capacitor right at its power pins. I'm not arguing with the suggestion, just unpacking t for my own enlightenment, and giving it some thought it would make life a bit easier.

Wayne

East London
South Africa

 

  • No, I am not an Electronics Engineer, just a 54 year old hobbyist/enthusiast
  • Yes, I am using Proteus to learn more about circuit design and electronics
  • No, I do not own a licensed copy of Proteus, I am evaluating it legitimately
  • No, I do not believe in software or intellectual property piracy or theft
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I think that you are being too literal with "every chip shall have a decoupling capacitor right next to it".

 

I've worked on a lot of big mostly TTL boards and I would phrase it as...

 

"Provided that you have followed good engineering practice with the routing of your power traces there shall be the same number of decoupling capacitors as there are chips."

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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On the idea of using the GND pin of an adjacent TTL chip instead of the GND leg of the chip the bypass capacitor is attached to's VCC pin, does this not defeat the purpose a bit, because the bypass capacitor is no longer at the power pins of each chip but rather sort of stitched across the board between chips

If you look at my post #2, you can see you are right on the money!! In #2 , they are super-fanatical and "worrying" about whether to put the via on on side of the SMT pad or the other to get the lowest inductance!!! How much is that 1 millimeter?  So they are trying to scrape it down to the bone.  That shows how far you can take it.

What you talk about (adjacent chip) is the other extreme...how far away can you get?   You prob get some improvement, but throw most of the highest freq goodness (hi freq filtering) in the trash.

The problem is, that things may work perfectly fine with NO cap (especially with simple little gates), so you can't tell the amount of degradation this long-arm hookup gave, compared to the best hookup.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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WayneZA wrote:
... and produce a home-made single-sided PCB.
Leaving the bottom-side etch resist enables a ground plane though easier for SMT.

WayneZA wrote:
Obviously when working with breadboards and Veroboard I don't have much flexibility, so I will place the bypass caps close to the VCC pin and then run as short as possible a jumper or link to GND from the other side of the capacitor.
Similar method for BusBoard SMT.

WayneZA wrote:
TTL are not the only integrated circuits I have encountered this on as I'm sure you guys must know, just the ones that easily spring to mind for the purposes of my questions.
CMOS has greater variety and increased hysteresis.

Some CMOS reduce ground bounce and overshoot and is a better impedance match to cables (transmission lines, driver current source and sink will sequence between a few values)

WayneZA wrote:
because the bypass capacitor is no longer at the power pins of each chip but rather sort of stitched across the board between chips Just asking as my limited understanding on the subject is that each chip required its own bypass capacitor right at its power pins.
That stitching increases the PCBA's resonant frequency (that's good)

 


Veroboard | Stripboard | Original Prototyping Board |Matrix

 

Surface Mount Prototyping PCBs | BusBoard Prototype Systems

BPS-DAT-(SMTpads)-Datasheet.pdf (page 7)

 

Bypass Capacitor Sequencing by Dr. Howard Johnson

...

...

[beginning of third paragraph above Figure 3]

So, if the layout in Figure 1b does not work well for modern high-speed digital devices, why do reasonable people still recommend it? I believe the main reason is that it worked beautifully on old two-layer boards. ...

 

edit :

Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices (Texas Instruments)

[page 14]

4 Design Issues and AUC Logic Solutions

4.1 Signal Integrity at Faster Speed

[near end of first paragraph]

In addition to the requirement for better signal integrity and faster speed, system designers, especially for portable applications, need a solution that requires no external termination, i.e., damping resistors, clamping diodes, pullup resistors, etc. Additional components use valuable board space, where space also is at a premium in portable applications. ...

 

edit2 :

Power Plane Resonance by Dr. Howard Johnson

[end of fourth paragraph]

If the driver continues to act in a repetitive manner (like a clock), the reflected noise builds to a significant degree. This behavior is called a "resonant mode" in the power system. In severe cases, resonance in the power system can cause your product to fail to function.

 

[VNA to measure the resonances]

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Tue. Sep 20, 2022 - 07:07 PM
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WayneZA wrote:
On the idea of using the GND pin of an adjacent TTL chip instead of the GND leg of the chip the bypass capacitor is attached to's VCC pin, does this not defeat the purpose a bit

If you think of your ground as a matrix running all across the surface of the board, running the cap GND side to the nearest point of that matrix may introduce less inductance than running the cap GND side to the chip ground point.  It's all about keeping the inductance down.  Much will depend on the actual ground layout, and the size of any ground traces.

 

BTW, I hand-wired a whole lot of stuff using TTL in the past, including complete CP/M computers with video boards, using bypass caps at Vcc and just a wired criss-cross for ground, and they always ran reliably.  I never had the feeling that it was a super-critical issue.

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The issue around capacitor placement is inductance and current flow. You want the low impedance for current spikes to be between the power/ground pins of each device. That is the principle. The question is how to achieve that. The problem with inductance is that it prevents the capacitor from doing its job. Inductance comes from lead/wire/trace length. So, here are some situations and what is good or bad about each. Remember, in this case, goodness or badness is relative!

 

1. Ceramic capacitor with long leads between diagonally opposite corner pins of IC ... long leads have inductance, more than you might appreciate. Not so good.

 

2. Good ground plane and through-hole capacitors ... A lot better because the ground plane offers low inductance between the cap and the IC ground pin. Place the cap close to the power supply pin and you are good.

 

3. Good ground plane and SMT caps ... better still since the internal inductance of SMT caps is quite low. Here, it becomes important to minimize the trace length from the cap to the power pin and to minimize the length of the trace between the cap and the ground via. 

 

4. Leaded caps on a board without a ground plane (just point-point traces) ... can be on par with (1) but there is another effect that can surprise you. It is called "mutual impedance" or more simply shared current path. When there is inductance, voltage spikes are generated between the ends of the inductance when there is a current spike. If you share the trace (or wire) from cap to ground pin with another device, then the noise from that other device can be injected into the one you are trying to bypass. Thus, you should have a dedicated set of traces or wires for each bypass capacitor.

 

The nagging question in all this is: how good is good enough? Those pictures of ground vias built right into the capacitor ground pad are for microwave and really fast logic (say, 1ns rise times and better). For circuits with clock rates up to 25MHz, you do not need to worry about that level.  Traces as long a cm from IC pin to cap or cap to ground will not kill you. 

 

The other part of this "how good is good enough" depends on WHY? Are you trying to meet CE emissions and susceptibility requirements or just trying to insure that you personal project works the way it is supposed to? If the latter, then trace + lead lengths between the power pin and the ground pin of 2-3 cm will probably be OK (unless you are doing a LoRa antenna matching circuit, lets say, then its a different ball game).

 

As for actual layout, here is how I used to do through-hole corner-corner bypass caps on dip packages. It makes NO difference which end of the cap has the long lead (for non-CE applications)!

 

 

 

Jim

 

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Sat. Sep 17, 2022 - 08:38 PM
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It is normal to talk about ceramic types today, but one from the recent past should not be forgotten.

 

Probably best 0.1u-money-can-by is marked .1M100 MMK EVOX which means 100V 0.3 spacing Rifa cap for LS/CMOS boards with DIP chips.

Metalized polyester, low ESR, superb temperature and ageing, I do not know other data (resonant freq or inductance).

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grohote wrote:

It is normal to talk about ceramic types today, but one from the recent past should not be forgotten.

 

Probably best 0.1u-money-can-by is marked .1M100 MMK EVOX which means 100V 0.3 spacing Rifa cap for LS/CMOS boards with DIP chips.

Good quality products always used that kind of Caps. Since we’re moving to SMD,the ceramic SMD cap as most used in the kits.

www.tokopedia.com/madagang .Buy and Donated cheap electronics and manuscripts.

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WayneZA wrote:

Generally peaking I will build a circuit on breadboard(s), then if it works as expected or I want to do more development I transfer it to Veroboard (my preferred more permanent development board), and then I will design and produce a home-made single-sided PCB. sometimes I will leave the circuit on Veroboard if it does not require refinement in the form of a PCB. I use the laser printer toner transfer method, etch with HCL and H2O2 and drill the board myself using a Dremel clone and a small Dremel workstation drill press, so double-sided boards are a bit of a stretch for me.They are possible but not trivial, hence my use of single-sided boards.

 

For decoupling purists, there used to be parts like this (still available on ebay) 

 

 

Those are designed to use the same holes and sit under the package, so you have very short leads and a low inductance loop.

Of course, they are not cheap, but they are impressive  :)

 

As general design, the convention of near VCC is easy and future-safe, as you may decide to copper GND plane the unused side, and suddenly that lowers your GND inductance numbers. 

 

You can buy vero board with a ground plane, and you might decide to run some boards thu the low cost Asian PCB makers.

 

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Who-me wrote:

For decoupling purists, there used to be parts like this (still available on ebay) 

 

 

Those are designed to use the same holes and sit under the package, so you have very short leads and a low inductance loop.

Of course, they are not cheap, but they are impressive  :)

 

I also remember decoupling capacitor units that ran the entire length of the board.  They stood maybe 1cm tall, obviously two metal strips with a dielectric in between, all encapsulated, with legs from both metal strips connecting to the PCB power and ground at regular intervals.  Just a very long linear capacitor with multiple leads.

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There were also sockets that included the cross-corners caps (normal leaded caps, hardwired)

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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avrcandies wrote:

There were also sockets that included the cross-corners caps (normal leaded caps, hardwired)

Ah yes, for breadboards those could be useful.

I recall making those using machine screw sockets, which have enough exposed metal on the top side to solder the cap leads to.

We also made some machine screw decoupled parts, using 2 SMD caps, one end of each solders to VCC and GND top side exposed metal, and then 2 fine wires link the other ends. Gives 2 parallel decoupling pathways.

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Ah yes, for breadboards those could be useful.

Well, yes, for any board.  Many many boards were fully socketed....lotsa chip replacing going on, perhaps.

Sometimes you'd see only every few chips with a cap (stingy).

r

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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avrcandies wrote:

Sometimes you'd see only every few chips with a cap (stingy).

r

 

I’d took the caps also the white MKM cap for TTL projects.

www.tokopedia.com/madagang .Buy and Donated cheap electronics and manuscripts.

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avrcandies wrote:
chips with a cap

 

This particular cap I remember from some TI boards, but not 0.1u- it was 47nF instead.

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grohote wrote:
This particular cap I remember from some TI boards, but not 0.1u- it was 47nF instead.
yes

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To be 47nF, or not to be, that is the question. In the size of 0805, they are the same, also 0603. Does anyone use 47nF, I do not know why the 0.1 must be a law.

 

But, I am sure that many 47nF plus one 10uF tantalum can be an answer.

 

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47nF or 100nF? It makes no difference. 

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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grohote wrote:
Does anyone use 47nF, I do not know why the 0.1 must be a law.
I noticed that big ICs at TI boards always had white 104 MKM meanwhile the TTL(14/16 DIPs) had above caps.

www.tokopedia.com/madagang .Buy and Donated cheap electronics and manuscripts.

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grohote wrote:

To be 47nF, or not to be, that is the question. In the size of 0805, they are the same, also 0603. Does anyone use 47nF, I do not know why the 0.1 must be a law.

 

But, I am sure that many 47nF plus one 10uF tantalum can be an answer.

 

In the past I've seen 47nF quite often.  Nothing magical about 100nF.

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kk6gm wrote:
In the past I've seen 47nF quite often. Nothing magical about 100nF.

 

To be discussed here: does CMOS/HC use more peak current than LS. Seems that 47nF was satisfactory for LS, is it also today on ahc/avc/all-other, wonder.

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 I do not know why the 0.1 must be a law.

Sometimes 0.1 is actually trouble, due to resonance, but this is typically not investigated (ignored).  There was an EDN article about this some years ago.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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The value of the capacitor is a lot less important than you might imagine. There is another factor that really is a lot more important, but usually over-looked or not understood: self resonance. Let me try to explain...

 

Every capacitor has inductance. This inductance is made up of the lead inductance and the inherent internal inductance, The old wound film capacitors were among the worst. Among the best are small-value SMT ceramic caps. Large value "aluminum" electrolytic caps tend to be pretty poor while tantalum electrolytic caps are pretty good. Large value SMT ceramic caps are a lot worse than the small value ones (but they are still pretty good compared to aluminum electrolytics.  

 

The most important factor, in all this, is not just the series inductance" but the self-resonant frequency. The capacitors capacitance and the capacitors inductance appear in series. There is a frequency, called the self-resonant frequency, where the reactance of the capacitance (impedance, if you want) is just equal and opposite to the reactance of the inductance. At this frequency, the inductance and capacitance cancel each other, making a series impedance of ZERO (except for any internal resistance). Below this frequency, the capacitor looks like, well, a capacitor with impedance that decreases as the frequency increases. Above this frequency, it looks like an inductor and the impedance of the capacitor increases with frequency. This frequency occurs at F = 1/2*pi*sqrt(L*C)

 

Now, this may seem like a lot of hand waving, but it has a very important impact. It explains why a 1uF bypass cap might actually be worse than a 0.1uF (100nF) in bypass applications. First off, the inductance of a 1uF cap is almost always quite a bit higher than the inductance of a 0.1uF cap of almost any construction. The capacitance is 10 times larger, so this makes the larger cap have a series-resonant frequency that is lower by 3X or more. The chart, below plots the impedance of 4 capacitors, 0.1uF (100nF), 10nF, 1nF, and 0.1nF (100pF).

 

What does all this mean? It shows that if your circuit needs to have effective bypassing above 20MHz, you should use something smaller than 0.1uF (100nF)! ICs such as most AVRs generate current spikes that are no wider than 3nS which means the frequency content starts at around 100MHz and goes up from there! If you are using anything larger than 10nF, it is not doing much for those narrow current pulses! But, if you are using 74C or 4000-series logic, that 100nF cap may be just fine.

 

Now, in most small MCU or logic systems, that cap close to the chip is important, but it is NOT good enough, on its own. You will also need some "bulk" capacitance. This means a few caps in the 1uF to 10uF range. If you have analog components (linear voltage regulators, op-amps, and such), the manufacturer will usually recommend particular capacitors in particular locations; FOLLOW those recommendations! Switch mode power converter manufacturers will recommend specific parts with a specific board layout: FOLLOW those recommendations.

 

[EDIT]

If you have slow, high current, elements such as relays, motors, and such, then the bulk capacitance should be even larger, such as 100uF or higher.

[/EDIT]

 

Jim

 

Courtesy: flexautomotive.net

 

 

 

 

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Tue. Sep 20, 2022 - 07:42 PM
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I couldn't find exactly what I was looking for, but something close:

 

 This issue first came to my attention in a project where a parallel resonant frequency of some paralleled rail bypass capacitors turned out to be 16 MHz for a gate array that was clocking itself at 16 MHz. What happened as a result is perhaps best left to the imagination.

 

As Jim says--there are a lot of considerations, just "throwing in a value" often works, but occasionally you can get bit (badly)

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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ka7ehk wrote:
The most important factor, in all this, is not just the series inductance" but the self-resonant frequency.

...

At this frequency, the inductance and capacitance cancel each other, making a series impedance of ZERO (except for any internal resistance).

low Q bypass capacitors for digital

ka7ehk wrote:
ICs such as most AVRs generate current spikes that are no wider than 3nS which means the frequency content starts at around 100MHz and goes up from there!
AVRxm are the exception among AVR.

 


Operating Above Resonance by Dr. Howard Johnson

[mid-page]

Figure 1—Magnitude and phase of real-world bypass capacitor

[end of second paragraph after Figure 1]

As plotted in the figure, over the range of 1 MHz to 100 MHz, this capacitor maintains an impedance of 1 Ω or less. That's good enough for most digital work. From 1 to 100 MHz, one hundred of these babies would give us our 0.01 ohms. Note that at 100 MHz we would be using this bypass component more than an order of magnitude above its series resonance frequency. That's okay. That's the nature of the bypass capacitor application.

A rule is the fifth harmonic is good enough; 100 MHz / 5 = 20 MHz square wave (AVRe+, AVRxt minus AVR Dx though AVRxt has slew limiting except for AVR Dx CLKOUT; PCBA-wide fast-edge clock signal is the primary EMI/EMC issue so partition the design by slew [try to keep fast edges within IC])

Capacitor manufacturers have web apps to plot impedance.

SimSurfing (Murata Manufacturing)

KEMET K-SIM 3.0

Quality Factor by Dr. Howard Johnson

[sixth paragraph]

Now comes the application I care most about: bypass capacitors for high-speed digital products. Depending on your power-system architecture, these bypass capacitors must cover a range of frequencies—from a few megahertz to several hundred megahertz, providing a low-impedance connection between power and ground all across that band. For that purpose, pick the smallest package (smallest inductance) your manufacturing people will let you use, and in that package size choose the largest value of capacitance you can reliably purchase from multiple vendors.

[end of seventh paragraph]

ordinary, garden-variety, low-Q capacitors will work better in your digital application. High-Q capacitors exacerbate resonances in a circuit, and resonance is the last thing you need in a power-distribution system. Digital folks want low-Q capacitors.

Series Resonance by Dr. Howard Johnson

Many digital systems suffer excessive power-supply noise at frequencies relating to the system clock. Could a series-resonant circuit, such as the one in Figure 1, connected between the power and the ground planes attenuate that noise? The answer can be yes, but only if your circuit satisfies the following improbable conditions.

[constant clock frequency (AVRxm and AVRxt are the frequency-agile AVR)]

[precision capacitors]

[no sleep]

[fixed PCB layout (earlier PCBA passed EMC whereas later variant doesn't)]

[bypass capacitors are effective on clock's harmonics (right ...smiley]

[last sentence]

A digital-power system is better served by lots of large, simple, nonresonant bypass capacitors.

 

ATxmega128A1U, ATxmega64A1U Data Sheet

[page 122]

Table 37-65. SPI timing characteristics and requirements.

[SPI clock rise and fall duration is 2.7 ns typical, 2.5 ns minimum? or 2 ns minimum?]

AVRxm EBI clock (internal) is 64 MHz typical; AVRxm SDRAM clock is an external signal.

AVRxt AVR Dx lack EBI which does ease EMC.

How XMEGA AVR can excite a VCC regulator instability (though a different AVRxm) :

XMega SRAM slow turnaround? - Solved (Glitchy Power Supply). | AVR Freaks

 

"Dare to be naïve." - Buckminster Fuller

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Howard Johnson knows well what he writes about. He is far more the expert than I am.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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WayneZA wrote:
should I be placing the bypass capacitor close to VCC and running a short track or trace to GND

+1

 

https://www.signalintegrityjournal.com/blogs/12-fundamentals

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