boot lock modes and interrupts

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Hi all,

In the application note AVR109 table 1 the description of mode 4 is "No read access (data or interrupt execution) from the other section."

My interpretation of this is that I can't interrupt code running in the boot section if the interrupt vectors are located in the app section. In other words, if there is a common function located in the bootloader (CRC in my case) it can't be interrupted even if it's called from the app section if the interrupt vectors are located in the app section.

Did I make it clearer or more confusing?

Could this be the case? Why would anyone want it that way?

Or do they mean that an ISR located in the boot section can't be executed from an interrupt vector in the app section?

Please tell me I'm completely wrong...

What I really wonder is if code in the boot section (not using SPM) is possible to interrupt with vectors and ISR in the app section while using boot lock mode 4.

/Janne

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According to my reading of the most recent ATmega8 datasheet, table 86 on page 222, I'd be inclined to believe that your interpretation is correct: While BLB02 is programmed, if the interrupt vectors are set to reside in the Bootloader section (via the IVSEL bit), then no interrupts will occur while PC is pointing to the Application section.

Similarly, while BLB12 is programmed, if the interrupt vectors are set to reside in the Application section (via the IVSEL bit), then no interrupts will occur while PC is pointing to the Bootloader section.

Why would they do it that way?
For the case of interrupts residing in the Application section while the Bootloader is running, it is easy to see the rationale that some designers might want as much protection as possible against accidentally executing incomplete software in the Application section while the Bootloader is in the middle of rewriting it.

Making the converse true too probably just makes sense from an orthogonality perspective, and may even reduce the complexity of the silicon.

In your case, you appear to have a potentially time-consuming function that you want to share in common between the bootloader and the application, and you want to ensure that high-priority interrupts from the application are still given a chance to execute while the shared function is running.

The solution, it seems to me, would be to ensure that BLB12 is never programmed - ie, never use BLB1 modes 3 or 4. I don't think that solution would pose a huge risk in terms of the potential for incorrect program execution, as long as you ensure interrupts are initially disabled through manipulation of the I-bit in SREG before entering any SPM-based routines.

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It seems to be directly related to LPM for some reason. It may be required by silicon, or there may be some way to use the irq's to 'bypass' security on doing an LPM to the other section in mode3 and mode4.

Maybe you could 'walk' the other section looking for an LPM, using the spm irq, taking advantage of the fact that 1 instruction will execute after irq's are enabled- so you can execute 1 instruction, and get back to the spm irq.

//just thinking
setup Y pointer to start of ram
setup Z pointer to a know byte in flash
setup X to bootloader address

spm irq address:
store r0 to ram
inc X
inc Y
make sure X Y in range yet
reset stack pointer
set r0 to 0x55
push bootloader address (X) on stack
enable spm irq
reti

now one instruction will execute after the reti
then back to the spm irq

when no more bootloader to see
or no more ram, dump ram out and go looking
for the known byte Z was pointing to

eventually you may be able to find an LPM in the other section, then its just a matter of doing it all over again, except now you can just push that LPM address before the reti, and get a read of any address (whatever you set Z to).

I haven't thought it all through, but disabling irq's when I'm in the other section would put an end to my fun.