Umm... after I finish my TCP/IP stack on UC3A I am soon going to revisit my project on bldc motors :)
I ended up successfully spinning my bldc motor using atmega164 up to 76K rpm. This was the limitation due to the max PWM freq and the BEMF ADC sampling I could generate with that chip.
I now I am thinking of redoing the project using atxemga...there the ADC sampling freq is 2MSPS and the PWM can surely go higher as the chip operating freq is 32MHz (max).
I am a little confused however how to utilise the timer counter interface of atxemga in order to drive the 3 phase (3 pairs) of PWM signals to the motor...
Previously with atmega164 I used one timer for PWM and changed the 6 ouput pins to suit my offsetted outputs and also had an AND gate there to only switch the top 3 sides using the PWM.
I see that atxemga has 3 timers that I could use to drive the 3 pairs of outputs without using the external AND gate...am I correct? How will I then create the offset of 60 degrees between the firing of each phases using the 3 timer counters? Arnt they all from the same input clocks?