Bit Rate Generator Unit

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Can anyone explain to me this passage please ?

 

Why the equation is like shown below and i also feel contradictory when i see this two sentences marked by orange and yellow?

 

 

I am living to bring up new earth ,and not to eat and destroy earth.

Last Edited: Fri. Jun 21, 2019 - 11:49 AM
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Where is the contradiction?

 

As a slave the receiver is clocked by SCL; to be able to decode the bits it is simply saying that the CPU clock must be 16 times SCL.

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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I don't see a contradiction. It's saying that when an AVR acts as slave then the local settings for bit rate are ignore. But what it's also saying is that when a slave the TWI frequency is dictated by the other end so it's maybe operating the link at 100kHz or 400kHz or something and that there is a requirement in the slave that its own F_CPU speed should be x16 or more. So say the I2C is being driven by the other end at 400kHz then this receiving AVR must be clocked at 6.4MHz or more.

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That's okay ,I understand it now ,could you tell me please why equation of clock is like shown above 

I am living to bring up new earth ,and not to eat and destroy earth.

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Because the I2C signals need to be synchronised to the internal clock and there's probably a glitch filter and a state machine. As to why 16 rather than 2 or 32 etc, well we don't know - that's internal to the chip. The datasheet tells us to not exceed it, so we must obey.

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Thanks for explanation ,could you tell me please why equation of clock is like shown above 

I am living to bring up new earth ,and not to eat and destroy earth.

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Which AVR is this?

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The equation really just comes down to a divisor based on the prescaler, the bit rate and a constant. We can already deduce that the TWI machine needs 16 clocks per bit. You also need a reasonable range of scaling to cope with the highest clock frequency and a lower one. What would you do if you were designing a similar peripheral?

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In terms of the equation, you are just creating a divider.  Many times a table is used instead for a selection:  1,2,4,64,128,512,2048  ...in this example an equation probably won't work well, since the values skip.

For your example, they were able to match the selections to a nice equation....you could always use it to make you own table in Excel.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Sometimes you just have to accept things are the way they are 'just because.'

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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I sat and puzzled over 4^TWPS in:

 

 

myself so then (as we don't yet know which AVR the above is from) I just took a look at a 328P datasheet and it has:

 

 

That seems much more like what I would have expected. I don't think anyone would be hugely surprised or confused by that formula. So I do wonder if the "4 to the power of" is some kind of formatting fault in the quoted datasheet?

 

With this 328 formula then if the CPU is running at 16MHz and you arbitrarily set TWBR to 3 and pick /4 for the TWPS bits in TWSR then the SCL frequency would be:

 

16000000 / (16 + (2 * 3 * 4))

 

16000000 / 40

 

= 400kHz

 

I guess if you thought that was too much you could increase TWBR or use a larger prescaler (I guess the two are split for coarse/fine adjustment?)

 

If the formula has really been 4^TWPS then I suppose the sums would have been:

 

16000000 / (16 + (2 * TWBR) * (4 ^ TWPS))

 

16000000 / (16 + (2 * 3) * (4 ^ 4))

 

16000000 / (16 + 6 * 64)

 

16000000 / (16 + 384)

 

40kHz

 

Still intrigued to know which AVR it is

 

EDIT: and it's worse because 4^4 is not 64 (where did that come from??) it is 256 in fact !!

Last Edited: Fri. Jun 21, 2019 - 04:37 PM
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So I do wonder if the "4 to the power of" is some kind of formatting fault in the quoted datasheet?

Possibly....or they wanted to be able to generate the following divider "factors", using as few selection bits as possible (2 bits of some config register), to give a wide range

0   ===> 1

1   ===> 4

2   ===>16

3   ===>64

On the other hand, wouldn't be surprised if it were an oooops.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Fri. Jun 21, 2019 - 05:24 PM
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avrcandies wrote:

So I do wonder if the "4 to the power of" is some kind of formatting fault in the quoted datasheet?

Possibly....or they wanted to be able to generate the following divider "factors", using as few selection bits as possible (2 bits of some config register), to give a wide range

0   ===> 1

1   ===> 4

2   ===>16

3   ===>64

On the other hand, wouldn't be surprised if it were an oooops.

 

 

That's exactly why they did it that way. I'm quite sure that the formula comes from the AT92USB646.

Last Edited: Sun. Mar 7, 2021 - 01:24 PM