Best way to wait for frequency stabilization on SAMD21?

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I've created an ATMEL Start project for the SAMD21.  The clock chain is:

 

XOSC32K => (32KHz) => GCLK3 => (32KHz) => DFLL => (48MHz) => GCLK0 => (12MHz)  => CPU and SERCOM:

 

 

This works, but on startup, the first string printed out by the SERCOM is gibberish -- thereafter it's fine.  My guess is that the DFLL takes a while to stabilize.  (Although, FWIW, when I've been running in the debugger and quit the debugger, the first string prints out without error.) 

 

If that's the case, what's the approved technique for waiting for it to stabilize?  Or -- if there's some other cause -- what's a good remedy?

 

This topic has a solution.

- rdp

 

Last Edited: Tue. Sep 7, 2021 - 03:22 AM
This reply has been marked as the solution. 
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Solved.  It wasn't the DFLL, it was XOSC32K that was causing trouble.  I upped the XOSC32K startup time from 122 uS to 1068 uS and it now starts up cleanly.

- rdp