basic instruction set listing?

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I'm looking for an AVR instruction set listing with only real instructions listed.
The AVR instruction set manual has extra "instructions" that are just aliases for other instructions.
For example clr r0 is just an alias for eor r0, r0.
While other instructions that seem to do the same thing are not aliases (dec r is a different instruction than subi r, 1).

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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So why can't you just take a highlighter and cross off that double handful?

What kind of work are you doing where this "feature" becomes important?

Are we then going to ban CLR, just as with banning "snarky"?

There are indeed fairly extensive threads and attachments, where the AVR instruction set has been analyzed w.r.t. unique op codes, as well as instruction encoding lists/charts by op code. Try searching them out.

Then, once you get your perfect list of op codes, tell me how you will sort into legacy vs. current models; Mega vs. non; brain-dead; Xmega.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Quote:
While other instructions that seem to do the same thing are not aliases.

You didn't provide enough information but IMHO the answer is NO.
I have never heard about such list.
Depending on your personal definition of "real instruction" there may be 2^32 op-codes down to perhaps 30 so the range is quite wide.
Quote:
dec r is a different instruction than subi r, 1

because dec does not affect SREG_C or because of some other reason?
And what about andi r,0 and clr r? No SREG differences here. Different for you?

No RSTDISBL, no fun!

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Brutte wrote:

And what about andi r,0 and clr r? No SREG differences here. Different for you?

Different, not just for me, but for real.
compile clr r and you'll see it compiles to eor r,r.

The reason I want a condensed list is I don't want the clutter of alias instructions when I'm searching through the instruction set to see if there is one that does what I want.

From the sounds of it, I'll have to make my own cheat sheet.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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One of the earlier discussions, with the thread containing Jeremy Brandon's list:
https://www.avrfreaks.net/index.p...
No explicit mention of the duplicates.

In this thread, Cliff comes up with 75 unique opcode patterns, which comprise the '131 powerful RISC instructions" seen in the datasheets. lol List of duplicates there, too.
https://www.avrfreaks.net/index.p...

Other links with mentions:
https://www.avrfreaks.net/index.p...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Quote:
Different, not just for me, but for real.

And why is that so, when these give exactly same results?
Are you suggesting a mov p,p is different than mov q,q, rjmp pc+1 or nop?

No RSTDISBL, no fun!

Last Edited: Sat. Feb 15, 2014 - 04:46 PM
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Quote:

From the sounds of it, I'll have to make my own cheat sheet.

After compiling the links above for you -- I don't think so. :twisted:

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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If an instruction is an alias then the instruction manual will tell you that.(under the upcode).

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An example of two that could be handled with a single instruction but aren't are adiw and sbiw. They have different opcodes, but sbiw could be done with adiw and a negative constant.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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theusch wrote:
One of the earlier discussions, with the thread containing Jeremy Brandon's list:
https://www.avrfreaks.net/index.p...
No explicit mention of the duplicates.

In this thread, Cliff comes up with 75 unique opcode patterns, which comprise the '131 powerful RISC instructions" seen in the datasheets. lol List of duplicates there, too.
https://www.avrfreaks.net/index.p...

Other links with mentions:
https://www.avrfreaks.net/index.p...

Quote:
bobgardner wrote:
How many opcodes are unused?
I counted 1682.

Thanks. Those reference are helpful.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Brutte wrote:
Quote:
Different, not just for me, but for real.

And why is that so, when these give exactly same results?
Are you suggesting a mov p,p is different than mov q,q, rjmp pc+1 or nop?

Look at the opcodes in the instruction set manual.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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The attached file was compiled by someone here quite a while ago (maybe Cliff) and updated by me a little more recently. It likely does not include more recently added opcodes for the xmegas and brain-dead tinys.

Quote:
The reason I want a condensed list is I don't want the clutter of alias instructions when I'm searching through the instruction set to see if there is one that does what I want.
What a BS reason. Surely the reason for the aliases is to make it easier to choose the proper opcode.

Attachment(s): 

Regards,
Steve A.

The Board helps those that help themselves.

Last Edited: Sat. Feb 15, 2014 - 05:27 PM
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I'm working with ATtiny AVRs with 8K or less, so I pared Cliff's list to 62 unique instructions:

0000 0000 0000 0000   nop            1
0000 01rd dddd rrrr   cpc     r,r      1
0000 10rd dddd rrrr   sbc     r,r      1
0000 11rd dddd rrrr   add     r,r      1
0001 00rd dddd rrrr   cpse    r,r      1
0001 01rd dddd rrrr   cp      r,r      1
0001 10rd dddd rrrr   sub     r,r      1
0001 11rd dddd rrrr   adc     r,r      1
0010 00rd dddd rrrr   and     r,r      1
0010 01rd dddd rrrr   eor     r,r      1
0010 10rd dddd rrrr   or      r,r      1
0010 11rd dddd rrrr   mov     r,r      1
0011 KKKK dddd KKKK   cpi     d,M      1
0100 KKKK dddd KKKK   sbci    d,M      1
0101 KKKK dddd KKKK   subi    d,M      1
0110 KKKK dddd KKKK   ori     d,M      1
0111 KKKK dddd KKKK   andi    d,M      1
100! 000d dddd ee-+   ld      r,e      1
100! 001r rrrr ee-+   st      e,r      1
10o0 oo0d dddd booo   ldd     r,b      1
10o0 oo1r rrrr booo   std     b,r      1
1001 000d dddd 0000   lds     r,i      2
1001 000d dddd 010+   lpm     r,z      1
1001 000r rrrr 1111   pop     r         1
1001 001d dddd 0000   sts     i,r      2
1001 001r rrrr 1111   push    r         1
1001 0100 0000 1001   ijmp            1
1001 0100 0SSS 1000   bset    S         1
1001 0100 1SSS 1000   bclr    S         1
1001 0101 0000 1000   ret            1
1001 0101 0000 1001   icall            1
1001 0101 0001 1000   reti            1
1001 0101 1000 1000   sleep            1
1001 0101 1001 1000   break            1
1001 0101 1010 1000   wdr            1
1001 0101 1100 1000   lpm     ?         1
1001 0101 1110 1000   spm            1
1001 010r rrrr 0000   com     r         1
1001 010r rrrr 0001   neg     r         1
1001 010r rrrr 0010   swap    r         1
1001 010r rrrr 0011   inc     r         1
1001 010r rrrr 0101   asr     r         1
1001 010r rrrr 0110   lsr     r         1
1001 010r rrrr 0111   ror     r         1
1001 010r rrrr 1010   dec     r         1
1001 0110 KKdd KKKK   adiw    w,K      1
1001 0111 KKdd KKKK   sbiw    w,K      1
1001 1000 pppp psss   cbi     p,s      1
1001 1001 pppp psss   sbic    p,s      1
1001 1010 pppp psss   sbi     p,s      1
1001 1011 pppp psss   sbis    p,s      1
1011 0PPd dddd PPPP   in      r,P      1
1011 1PPr rrrr PPPP   out     P,r      1
1100 LLLL LLLL LLLL   rjmp    L         1
1101 LLLL LLLL LLLL   rcall   L         1
1110 KKKK dddd KKKK   ldi     d,M      1
1111 00ll llll lsss   brbs    s,l      1
1111 01ll llll lsss   brbc    s,l      1
1111 100d dddd 0sss   bld     r,s      1
1111 101d dddd 0sss   bst     r,s      1
1111 110r rrrr 0sss   sbrc    r,s      1
1111 111r rrrr 0sss   sbrs    r,s      1 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Quote:

I'm working with ATtiny AVRs with 8K or less, so I pared Cliff's list to 62 unique instructions:

Can't be:
Quote:
• Advanced RISC Architecture
– 125 Powerful Instructions ...

;) much discussed in the links above

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
Quote:

I'm working with ATtiny AVRs with 8K or less, so I pared Cliff's list to 62 unique instructions:

Can't be:
Quote:
• Advanced RISC Architecture
– 125 Powerful Instructions ...

;) much discussed in the links above

:)
The ATtiny88 datasheet says:
– 123 Powerful Instructions
And the ATtiny85:
– 120 Powerful Instructions

but I can't see any difference, and I think the only way you count ~120 instructions is if you include the multiply instructions.

Maybe there's a seed of truth there, and the marketing folks are telling us that extra instructions like multiply are actually implemented in the ATtinys. ;-)

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Just a thought but a disassembler cannot know if a particular bit pattern means CLR R23 or EOR R23,R23 so the author presumably had to make a choice of how to annotate it (EOR Rn, Rn of course). It could therefore be illuminating to look at the source of some open source disassemblers (avr-objcopy, avra, disavr, etc) as they must effectively have "reduced lists" too.

Cliff

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clawson wrote:
Just a thought but a disassembler cannot know if a particular bit pattern means CLR R23 or EOR R23,R23 so the author presumably had to make a choice of how to annotate it (EOR Rn, Rn of course). It could therefore be illuminating to look at the source of some open source disassemblers (avr-objcopy, avra, disavr, etc) as they must effectively have "reduced lists" too.

Cliff

Good point. It looks like the instruction set manual was used. For example lsl says "16-bit Opcode: (see ADD Rd,Rd)". When lsl r0 is disassembled with avr-objdump -D, it says add r0, r0.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Quote:
When lsl r0 is disassembled with avr-objdump -D, it says add r0, r0.
Of course it does. How would the disassembler know which mnemonic was used when the code was assembled?

Regards,
Steve A.

The Board helps those that help themselves.

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Koshchi wrote:
Quote:
When lsl r0 is disassembled with avr-objdump -D, it says add r0, r0.
Of course it does. How would the disassembler know which mnemonic was used when the code was assembled?

Why are you asking a redundant question?

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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add r,r
alters carry
Many machines have logical left/right shift that does not alter carry, and arithmetic left/right shift (or rotate) that does alter carry.

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stevech wrote:
add r,r
alters carry
Many machines have logical left/right shift that does not alter carry, and arithmetic left/right shift (or rotate) that does alter carry.

I was looking for a shift without carry for some bitbang code. Shift followed by clc doesn't help in all situations, so it can end up being 3 instructions - in sreg, shift, out sreg

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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I don't know what you try to do. But if you want a shift "like" function you can often do it with skip on bit set/clr and have the code 8 times (unrolled).

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sparrow2 wrote:
I don't know what you try to do. But if you want a shift "like" function you can often do it with skip on bit set/clr and have the code 8 times (unrolled).

I've written a shift out function that doesn't touch carry with bst, bld, out (unrolled 8 times). If I understand your suggestion using sbrs/sbrc, that would take four instructions per bit instead of 3.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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No it would take the same, if you first set the bit and then check check if it should have been cleared.