...From AVR300

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This is from Atmel's AVR300 I2C ASM.

Tell me what this means?

"sbi DDRD,SCLP ; force SCL low

That's rhetorical, it means FORCE the clock port low. That's a port direction instruction and it = OUTPUT!

Rob

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Rob,

You create "Open-Drain" by writing 0 to PORTx.y
Then if DDRx.y == 1 the output sinks low.
If DDRx.y == 0 the pin is an input. Hence the output is pulled high by the external 4k7 pull-up resistor.

You will get the characteristic shark's fin on a scope. i.e. a visible exponential rise-time with a steep fall-time.

David.

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Quote:
That's a port direction instruction and it = OUTPUT!
You got it! But ONLY as long as you are transmitting a zero then you release the pin by
 cbi	DDRD, SCLP		; release SCL

after the bit time has expired.

By the way the code would be more portable if instead of using the DDRD port name at that point the actual port would be defined as part of a header ie

#define SCLP_DDR DDRD

and then just use

 cbi	SCLP_DDR, SCLP		; release SCL

etc. but it's old code so it's ok I guess for us elderly freaks. :-)

John Samperi

Ampertronics Pty. Ltd.

https://www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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ohh look what some clever person did years ago (2007) :wink:

;TWI equates
#define	I2C_port_out portb
#define	I2C_port_in pinb
#define	I2C_DDR_port ddrb
#define	SCL pb0						;I2C Clock bit
#define	SDA pb2						;I2C Serial data bit
#define	b_dir 0						;transfer direction bit in i2cadr
#define	i2crd 1
#define	i2cwr 0
i2c_rep_start:
	sbi	I2C_DDR_port,SCL		;force SCL low
	cbi	I2C_DDR_port,SDA		;release SDA
	rcall i2c_hp_delay			;half period delay
	cbi	I2C_DDR_port,SCL		;release SCL
	rcall i2c_qp_delay			;quarter period delay

so I guess my "fixed version" of AVR300 can be used on any port and any port bit too.

John Samperi

Ampertronics Pty. Ltd.

https://www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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RobDD wrote:
This is from Atmel's AVR300 I2C ASM.

Tell me what this means?

"sbi DDRD,SCLP ; force SCL low

That's rhetorical, it means FORCE the clock port low. That's a port direction instruction and it = OUTPUT!

Rob


Nobody has tried to tell you otherwise. Force the SCL(or SDA) low(PORT = 0, DDR = 1), go tri-state(DDR = 0) and let the pull-up do its job for a high. If you actually read the posts apart from your own, you'd have worked this out a while back. If there's any part of this you still don't understand, please ask.

Four legs good, two legs bad, three legs stable.

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Just to say that Philips have a great PDF to describe I2C. You probably should read it to understand how the bus is shared and why no device could drive the bus to a hard 1 as they'd just take over and control the whole thing to the exclusion of all others. The bus is based on the fact that it is 1 when it's not 0 :?