AVR SPI and ISP

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Dear AVRFreaks,

During my project I am going to make the PCB design, but before this I would like to ask you one simple question.

I am using the ATMega2560 at 5V Vcc. In my circuit the AVR SPI Port is simultaneously connected to :

- a series of CD74HC595 shift registers (5V Vcc)
- the ISP header (I am using the JTAG ICE mk2 and DRAGON)
- an SPI 3V3 exterbal flash (3.3V Vcc)

As you can see at the photos, there is a level shifting circuitry between the uC and the memory.

Will this circuitry have any negative effect to the ISP functionality ?

Any opinion is wellcome.

Thank you in advance.

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Michael.

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what you should do is make the circuit as follows:

the ISP programming connections should be connected directly to the processor.
from that add (I always use about 1K) series resistors to the rest of the system, I would split them separately. 1 resistor to the 5V section and a resistor to the 3V3 section.
but from the images posted you seem to be more or less doing that..
only not sure why your would need D3
and I think it might be unwise to have the transistor on the CS line. If the processor is in reset the line is input with pull-up this would mean that you have selected the dataflash and that might be interfering with your programming.

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Dear meslomp,

Thanks for your reply.

D3 is used as an external clamping diode.

Reading the datasheet/IO Ports unit, I see that all pins reset state is INPUT with Int. Pull ups disabled (DDRx = 0x00, PORTx = 0x00), this means that in reset state the external flash will not be enabled. Is there something else that I missed ?

but.....I am a liitle bit confused.

Do you think that the Memory side CLK, MOSI and MISO circuitries will cause any affect to the ISP functionallity ???

Thank you.

Michael.

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The SPI lines all go into 3-state when /CS is high.

So make sure that all boards are powered at the same time and that all /CS lines have external pull-up resistors.

This means that when you do ISP, all the other SPI devices are deselected.

I have not studied your schematic. Any AT45 devices should run at 3.3V. 5V is not allowed.

David.

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Dear David,

Thanks for your reply.

I can confirm that all CS are desabled during the ISP.

Because AT45DB081D run at 3.3V and ATMega run at 5V, I placed two voltage dividers and a level shifter (as a buffer) at the memory side, which uses the SPI lines.

My question is if these voltage dividers or the MOSFET based level shifter cause any bad effect to the ISP functionallity ?????

Michael.

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You need a external pull-down on MEMORY_CS line because Q1 inverts the signal.

I presume your AT45 is either/or. You can't have two AT45's with the same /CS.

Otherwise, everything looks fine to me. But I am not a hardware expert.

No, I can't see anything interfering with ISP.

David.

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ahhh.....now I got you. hahahaha.

Only one of the two AT45xxx is soldered on each PCB. I just gave the option of using an 8MBit or a 64MBit flash.

Quote:
No, I can't see anything interfering with ISP.

David, did you see the 2 Voltage dividers at the CLK and MOSI lines ??? That's why I am wondering for the ISP functionallity.

Any other opinions are wellcome.

Michael.

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Yes, I saw them. Yes they are a permanent 'load' on the SCK, MOSI lines. Your AVR will be quite capable of driving them. As will your ISP programmer.

Likewise, any other SPI slave will be able to drive the MOSFET load.

Personally, I would just run the whole system at 3.3V

I know that the AVR is not rated for 20MHz @ 3.3V. I bet that 99.95% of AVRs will run fine at this voltage. I would only worry if you have temperature extremes.

David.

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I have already tested all the other SPI circuits and can affort the permanent 1.5K load.

Michael.

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