AVR output curves

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I'm looking for output rise time curves for 3V3 and 5V supply into a hiZ load with 20-30pF of capacitance.  With my scope it seems to be around 3ns, but at 1Gsps, the sample resolution sucks.

I found some old threads talking about IBIS files, but I've never used them before.  I'm wondering if anyone has generated the curves for either the ATMega328P or the ATTiny85.

 

 

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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If you need ultra fast risetimes, you might want to add a buffer, so it is more tightly controlled & somewhat guaranteed to be speedy in transition.  There might be a lot of variation with the generic port pin if they are not optimized for speed.

 

Even this fast ECL output takes about a half ns for rise and fall

https://www.onsemi.com/pub/Colla...

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Wed. Jan 27, 2021 - 12:24 AM
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avrcandies wrote:

If you need ultra fast risetimes, you might want to add a buffer, so it is more tightly controlled & somewhat guaranteed to be speedy in transition.  There might be a lot of variation with the generic port pin if they are not optimized for speed.

 

Even this fast ECL output takes about a half ns for rise and fall

https://www.onsemi.com/pub/Colla...

 

 

 

I don't want faster rise times, I want to know more precisely how slow the rise time is.  I want to calculate how long a connecting ribbon cable can be before components have to be added for impedance matching.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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You need to start considering terminations when reflective signal paths are longer than 1/4 to 1/2 the signal rise time (one way propagation). Real circuit boards are around 1ns/foot. So, with a 1ns rise time, you don't need to worry until it gets about 6" long.

 

Note that there is NO hard-and-fast criterion. For an 8-bit MCU, inputs are generally sampled at the clock rate or twice the clock rate (eg, both edges). So, if it has a 10MHz F_CPU, you have at least 50ns for things to stabilize on a port pin after an edge. In actuality, you cannot get an output turned around into an input that quickly, so it is typically longer than that!

 

Note, also, that the port source impedance is not constant during a transition. So, it is not so easy to define "source impedance". You CAN identify a channel impedance for the ribbon, and that is rarely the same as the matched impedance of the port pin. So, you will almost never have a matched system at the source end.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Wed. Jan 27, 2021 - 05:40 AM
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ka7ehk wrote:
1/4 to 1/4
I know that is not what you intended Jim.

Ross McKenzie ValuSoft Melbourne Australia

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SHOULD have been 1/4 to 1/2! Will correct original.

 

Also need to add that you can rarely achieve a matched line at the far end, either, because of capacitance presented by the load (another port pin),

 

In the end, at operating speeds and conditions of common 8-bit CMOS MCUs, termination is pretty much irrelevant. So long as the signal does not depart from the target logic voltage by more than about Vc * 30% (depends on the logic specs), the receiving end will never detect that there are reflections. Example:

 

Assume: System Vcc = 3.3V. Target logic levels 0V and 3.3V.

 

So long as the logic low coming out of the transmission channel is between 0 and +0.99V, the receiver will never "know" that there is ringing or ripple. It is invisible to the receiver.

 

So long as the logic high coming out of the transmission channel is between +2.31V and +3.3, the receiver will never "know" that there is ringing or ripple. Again, it is invisible to the receiver.

 

Any voltages that exceed Vcc or drop below ground will be attenuated by the transient protection diodes that are part of most logic inputs.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Wed. Jan 27, 2021 - 05:57 AM
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ka7ehk wrote:
Any voltages that exceed Vcc or drop below ground will be attenuated by the transient protection diodes that are part of most logic inputs.

For your protection - EDN

by Dr. Howard Johnson

December 7, 2004

[beginning of third paragraph]

If you depend on ESD-protection diodes to clamp transients on a high-speed bus, you risk burning them out.

A bit of series termination aids and/or the external ESD suppressors that Howard mentions.

Some transient suppressor datasheets will have a formula for calculating the series termination.

 


Keyword Index | Signal Consulting (search on ESD)

The Art of Electronics 3rd Edition | by Horowitz and Hill

Download a sample chapter

[page 16]

12.1.5 Input protection 804

 

"Dare to be naïve." - Buckminster Fuller

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ka7ehk wrote:

Any voltages that exceed Vcc or drop below ground will be attenuated by the transient protection diodes that are part of most logic inputs.

 

Not for 5V tolerant IO on 3V3 parts.   STM32 parts are spec'd for 4V above Vcc on their 5V tolerant IO.

 

I have no special talents.  I am only passionately curious. - Albert Einstein