I finally read the datasheet details about ATmega32 interrupt priorities and will share here details learned. (Other devices may differ; not sure.)
If you enable interrupts in any ISR then that ISR can be interrupted by ANY interrupt no matter the priorities.
The priority is determined by the order of the vector addresses and determines which interrupt is serviced when two or more are waiting. (The lowest number is serviced first.)
Enabled interrupts that are scheduled while SREG is set to disable all interrupts will be serviced when global interrupts are enabled provided the individual interrupt wasn't cleared already by software.
One instruction of main code is executed between interrupts. I am not sure if this is correct: if the interrupted code is itself an ISR then the "one instruction" rule may apply there. Anyone know?
No doubt this is covered in the FAQs and I probably got something wrong. But perhaps someone will find this useful.