AVR Freaks

Thanks guys, yep, -fno-tree-loop-optimize also works. Btw, optimization level is -Os and gcc version is 4.8.1

Also, I didn't know I could set optimization options on a per function basis, so thank you also for this info

So I'll say my problem is solved with a code like this:

int main() __attribute__ ((optimize("no-tree-loop-optimize")));

int main() {
	byte mask=1, count=0;
	do
		if (PIND & mask) count++;
	while (mask <<=1);
	return count;
}

This generates the "proper" code, directly using the flags from the shift (actually, add) instruction for the branch

Sure, I understand. This is not my actual code, just a simplified example to illustrate the problem.

To do like you said, shifting the temp and adding the carry flag to a counter,  can not be done in C, right? Because you have no direct access to the carry flag from C. Or is there some trick I don't know?

Edit: Anyway, if I don't use the mask, I will need a loop counter that has to be decremented, so it would take about the same time. But the port read should be moved outside the loop, of course.

I'm really not very good with C, I'm an asm programmer at heart and even that is just a hobby. It's because I usually program is asm that I was distressed when I found gcc was de-optimizing code I always hear about how great optimizing compilers are...

I've checked the assembly output of that function, it also takes an int argument, so it wastes half its time adding zeroes when the argument is 8 bit sized.

And talking about non-portability :-) fully unrolled loop is asm:

 int main() {
	int result;
	asm (
		"clr	r24			\n"
		"in	r25, %1			\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"adc	r24,__zero_reg__	"
   		:"=r" (result)
		:"i" (_SFR_IO_ADDR(PIND)));
	return result;
}

I must stress I'm a gcc noob, so I'm not even sure this code is ok, seems so from the asm output. This inline assembly syntax really is awful, though, but I learned a lot just by trying to write it

I have, seems ok. If there is some mistake please point it out to me. Also, what you suggested is:

 int main()
{
	int result;
	asm (
		"clr	r24			\n"
		"in	r25, %1			\n"

		"lsr	r25			\n"
		"1:				\n"
		"adc	r24,__zero_reg__	\n"
		"lsr	r25			\n"
		"brne	1b			"

   		:"=r" (result)
		:"i" (_SFR_IO_ADDR(PIND)));
	return result;
}

edit: sorry, you were replying to the other guy

So the compiler really is quite smart, I need to choose the optimization options carefully, and also study this inline assembly stuff. I have learned much more from this thread than I was expecting, so tnx you all

However, I still found a new problem

Using this code (I know it's sub-optimal, it's just for illustration), in the end the compiler still clears r25 for the return value, even though it is inevitably already zero after 8 shifts. Is there a way to explain the compiler r25 does not need to be cleared again?

 int main()
{
	uint8_t result;
	asm (
		"clr	%[res]					\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__		\n"
		"lsr	%[arg]					\n"
		"adc	%[res],__zero_reg__	"
   		:[res] "=&r" (result)
		:[arg] "r" (PIND)
		);
	return result;
}

generates:

00000080 <main>:
                "adc    %[res],__zero_reg__             \n"
                "lsr    %[arg]                          \n"
                "adc    %[res],__zero_reg__     "
                :[res] "=&r" (result)
                :[arg] "r" (PIND)
                );
  80:   99 b1           in      r25, 0x09       ; 9
  82:   88 27           eor     r24, r24
  84:   96 95           lsr     r25
  86:   81 1d           adc     r24, r1
  88:   96 95           lsr     r25
  8a:   81 1d           adc     r24, r1
  8c:   96 95           lsr     r25
  8e:   81 1d           adc     r24, r1
  90:   96 95           lsr     r25
  92:   81 1d           adc     r24, r1
  94:   96 95           lsr     r25
  96:   81 1d           adc     r24, r1
  98:   96 95           lsr     r25
  9a:   81 1d           adc     r24, r1
  9c:   96 95           lsr     r25
  9e:   81 1d           adc     r24, r1
  a0:   96 95           lsr     r25
  a2:   81 1d           adc     r24, r1
        return result;
}
  a4:   90 e0           ldi     r25, 0x00       ; 0
  a6:   08 95           ret