ATXmega64A1-AU Getting started

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So I just got some of these chips last week and soldered one to a test board. Tested the JTAG and everything looks fine so far.

So I just started my first line of code and looking at configuring the osc from the default 2MHz to the 32MHz. I read the AVR1000: Getting Started Writing C-code for XMEGA and figured I will follow the guidelines.

so here it is:

OSC_struct.CTRL = (OSC_struct.CTRL & ~CLK_SCLKSEL_gm) | CLK_SCLKSEL0_bm;

but I wanted to use

OSC_struct.CTRL = (OSC_struct.CTRL & ~CLK_SCLKSEL_gm) | OSC_RC32MEN_bm;

which should be the same thing, except that the definitions are defferent in avr/iox64a1.h

Datasheet:

Quote:
Register Description - Clock
7.9.1 CTRL - System Clock Control Register
"¢ Bit 7:3 - Res: Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
"¢ Bit 2:0 - SCLKSEL[2:0]: System Clock Selection
SCLKSEL is used to select the source for the System Clock. See Table 7-1 for the different
selections. Changing the system clock source will take 2 clock cycles on the old clock source
and 2 clock cycles on the new clock source. These bits are protected by the Configuration
Change Protection mechanism, for details refer to Section 3.12 "Configuration Change Protection"
on page 12.
SCLKSEL cannot be changed if the new source is not stable.
Table 7-1. System Clock Selection
SCLKSEL[2:0] Group Configuration Description
000 RC2MHz 2 MHz Internal RC Oscillator
001 RC32MHz 32 MHz Internal RC Oscillator
010 RC32KHz 32 kHz Internal RC Oscillator
011 XOSC External Oscillator or Clock
100 PLL Phase Locked Loop
101 - Reserved
110 - Reserved
111 - Reserved

/* CLK - Clock System */
/* CLK.CTRL  bit masks and bit positions */
#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */


/* OSC - Oscillator */
/* OSC.CTRL  bit masks and bit positions */
#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */

#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */

#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */

#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */

#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */

Do I have to double check everything.

Grrrrrrrrr..........

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I figured it out, these are separate registers