ATXMEGA256A3BU JTAG pins no longer working

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djoshi
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Posted by djoshi: Tue. Jan 4, 2022 - 06:03 PM
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Hi 

 

I got a PCB that uses the XMEGA256A3BU with JTAG. I have been using this board for several months. But all of a sudden I can no longer program the board, I checked all the pins and found TCK and TDO have a resistance of about 10 ohms to GND,

 

Does this sound like a static issue?

 

 

Is there any way to get this XMEGA working again with JTAG?

 

 

Thanks

Regards

DJ

Tags:

AVR Microcontrollers, AVR and XMEGA, AVR040, ESD, Douglas C. Smith, jtag, ATxmega256A3BU
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gchapman
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Posted by gchapman: Tue. Jan 4, 2022 - 06:19 PM
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djoshi wrote:
Does this sound like a static issue?
Yes

JTAG cables are antennas, ESD damage is cumulative (air strike ESD adds up because the ESD suppressors aren't completely on)

 

P.S.

djoshi wrote:
XMEGA256A3BU
Am sorry for your loss.

 

Destroying Electronic Components from Across the Room With ESD | Technical Tidbit - May-June 2012 by Douglas C. Smith

ESD and Transients | AVR040: EMC Design Considerations

 

XMEGA Lead Time, Dec'20 | AVR Freaks

 

"Dare to be naïve." - Buckminster Fuller

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djoshi
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Posted by djoshi: Tue. Jan 4, 2022 - 06:33 PM
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So no choice apart from replacing the device now?

 

I think i have left the programmer plugged in few times while its not being used. 

Thanks

Regards

DJ

Last Edited: Tue. Jan 4, 2022 - 06:34 PM
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gchapman
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Posted by gchapman: Tue. Jan 4, 2022 - 06:58 PM (Reply to #3)
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Are pins 56 and 57 available (PDI)?

 

ATxmegaA3BU Datasheet (bottom of page 59)

 

"Dare to be naïve." - Buckminster Fuller

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djoshi
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Posted by djoshi: Tue. Jan 4, 2022 - 07:21 PM
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Pin 57 is connected to my RESET line and PIN 56 can be either have wire soldered to it.

 

 

If I am correct Pin57(CLK) connects to RESET wire on JTAG header and 56 to TDO wire on the JTAG header. 

 

So how is the PCB set to RESET if used by the PDI CLK?

Thanks

Regards

DJ

Last Edited: Tue. Jan 4, 2022 - 07:22 PM
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gchapman
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Posted by gchapman: Tue. Jan 4, 2022 - 07:43 PM (Reply to #5)
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djoshi wrote:
So how is the PCB set to RESET if used by the PDI CLK?
Isn't though the XMEGA can be reset via PDI.

 

XMEGA AU Manual

[bottom of page 115]

9.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers.

 

"Dare to be naïve." - Buckminster Fuller

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djoshi
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Posted by djoshi: Tue. Jan 4, 2022 - 07:47 PM
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If I am correct to use PDI, does JTAG need to be disabled first?

 

 

Thanks

Regards

DJ

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gchapman
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Posted by gchapman: Tue. Jan 4, 2022 - 07:51 PM (Reply to #7)
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IDK (will take some reading of the XMEGA AU manual)

 

"Dare to be naïve." - Buckminster Fuller

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gchapman
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Posted by gchapman: Wed. Jan 5, 2022 - 02:12 PM (Reply to #7)
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Yes

XMEGA AU Manual

[page 398]

32.4.2 Disabling

The JTAG interface can be disabled by unprogramming the JTAGEN fuse or by setting the JTAG disable bit in the MCU control register from the application code.

[page 400]

32.5.1 Switching between PDI and JTAG modes

The PDI controller uses either the JTAG or PDI physical layer for establishing a connection to the programmer. Based on this, the PDI is in either JTAG or PDI mode. When one of the modes is entered, the PDI controller registers will be initialized, and the correct clock source will be selected. The PDI mode has higher priority than the JTAG mode. Hence, if the PDI mode is enabled while the PDI controller is already in JTAG mode, the access layer will automatically switch over to PDI mode. If switching physical layer without powering on/off the device, the active layer should be disabled before the alternative physical layer is enabled

 

"Dare to be naïve." - Buckminster Fuller

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