ATXMega128A1U TWI Problem

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I have written a number of TWI routines for the AtMega series processors, but this is my first foray into TWI on an Xmega processor. In this application the ATXMega128A1U is acting as a slave. The master is an ASIC. There are only two defined transactions for the application: A single byte write from the Master to the Slave and a single byte read by the Master of the Slave. The slave contains 32 "mailbox" sub addresses. So, in a single write transaction the Master can write one byte to any one of the 32 mailboxes, or read one byte from any one of the 32 mailboxes. Sort of like a small EEPROM. The distance from Master to Slave is a few inches on a multi-layer PCB. There is only one other TWI device on the bus - a 24C32 EEPROM with which the Master can communicate flawlessly.

 

The AtxMega transactions are structured like this:

 

WRITE:

1st TWI Word: Device Address with Write Bit (0) ( Device address is 0x10)

2nd TWI Word: Mailbox address - 0x00 to 0x1F

3rd TWI Word: 8-bit Data to be written to the designated Mailbox.

(All words originate in the Master)

 

READ:

1st TWI Word: Device Address with Write Bit (0) ( Device address is 0x10)

2nd TWI Word: Mailbox address - 0x00 to 0x1F

3rd TWI Word: Device Address with Read Bit (1) ( Device address is 0x10)

4th TWI Word: 8-bits of data placed on the SDA line  by the Slave (ATXMega128A1U)

( First three words originate in the Master, fourth from the Slave.)

 

The Write transaction is working perfectly. So, I am confident that the TWI signals are properly functioning, pull-up resistors are appropriate values, etc.) It is the Read transaction that is giving me a problem.

Since this is my first attempt at writing TWI routines for an AtXMega I am using a polling approach rather than an interrupt driven approach so I can understand the AtXMega's TWI mechanism in as concise a routine as possible. I will later convert this to an interrupt driven form for the real application. The Write transaction routine I mentioned above is a polling routine and it works fine. Attached is the code snippet of my Read routine. I have also attached an O-scope picture of the SCK and SDA signals taken while the attached routine is running on the ATXMega128A1U. The Master is performing constant Read Transactions (in the format described above) at a rep rate of approximately 2 per second.

 

If you look at the attached scope trace it seems that my routine is accepting the 1st device address word from Master OK. The Master then sends the Mailbox Address in word #2, which my routine is properly capturing. My routine is also capturing the 3rd word (Device address + Read Bit) and the Master seems to be OK as well because it then pumps out the last packet of 9 clock pulses seen in the scope picture. However, notice that the SDA line is "silent" during this time period, being held at a constant high level. THIS IS MY PROBLEM: I can't get the ATXMega128A1U to drive the SDA line with the requested data. I load the data into the TWI Slave Data register, but it never seems to make it out of the IC and onto SDA!

 

Now, if you notice in my code snippet I have commented out the section of the routine that is intended to perform he last part of the Read transaction. Here's why: If I include this section of code, the Master performs one transaction then "quits". It finds some sort of "error" and does not continue to send the periodic Read transactions. I have captured this single transaction on the scope and find that the SDA line is indeed constantly high during the fourth set of clock pulses. On the other hand, if I do not include this fourth section of the transaction in my routine (I.e. comment it out), the Master will repeat the Read transactions forever, producing the signals (including the fourth set of clock pulses) you see in the attached scope picture.

 

Therefore I have focused my attention of the 3rd and 4th transaction steps in my routine. I have tried (it seems) every possible combination of Status Flags to poll, command bits to write to bits 0 & 1 of Control Register B, etc. All to no avail. Nothing I have tried will allow the data which I write to the TWI Slave Data Register to emerge onto the SDA line when the Master issues that last group of clock pulses in phase 4 of the transaction. In fact, I'm not even sure that when I write data to the TWI Slave Data Register that it is actually being written to the Data Register because of the split nature of this register. (There's a statement made in the AU Manual - Section "21.1.5 DATA - Data Register" - stating that "The DATA register can be accessed only when the SCL line is held low by the slave; i.e.,when CLKHOLD is set." My quandary: What does "access" mean in this context? Does it include writing data into the register? In other words, the register write operation is blocked by some kind of gating signal involving the CLKHOLD bit. A detailed block diagram of the TWI section of the AtXMega would probably go a long way here to complement the descriptions of the various TWI register bits and functions, like the diagram which is included in the UART section of the same AU Manual.

 

I should also mentioned that I have the two TWI pins configured as GPIO inputs prior to entering this routine. Am I correct in assuming the AtXMega's TWI subsystem will properly toggle the SDA line between receiving and driving as required by the current transaction? (That is, the reception of a Device Address match with the Read Bit set causes the TWI section to drive SDA rather than sense it. A far as I can tell there is no mention of this in the AtXMega literature.)

 

Any suggestions will be greatly appreciated! And Thank You for your time reading about my problem.

 

 

 

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Since I have received no comments on my original complete question, let me present a question about the kernel of the problem I am experiencing:

 

In the ATXMega128A1U TWI Controller what causes, prompts, or triggers the TWI Slave Data Register to drive its contents onto the SDA line using the SCK pulses generated by the Bus Master?

 

Is this supposed to happen automatically when the Slave receives a Read Command from the Bus Master? Or, is there some action that must be taken by the Slave's controlling firmware? Does the TWI Controller automatically cause it's designated SDA output pin to switch to output driving mode, or does the Slave's controlling firmware actually have to change the direction of the output pin to allow the Slave Data Register's data to drive the SDA line? It seems to me the explanations in the AU Manual's TWI chapter are silent on this point.

 

Thanks, Chuck

 

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what causes, prompts, or triggers the TWI Slave Data Register to drive its contents onto the SDA line using the SCK pulses generated by the Bus Master?

The R/W bit set to R and the clock pulses on SCK.  There is no need to switch the pin between input and output as SCK and SDA in both the Master and Slave have their direction set to OUTPUT and the mode to WIRED_AND_PULL.  The pin state can always be read, regardless of the pin direction.  Look at the AS/ASF example project Unit Test for the XMEGA TWI - A1U Xplained Pro (or something like that).

 

Greg Muth

Portland, OR, US

Xplained/Pro/Mini Boards mostly

 

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