ATtiny87/167 - 32 Reg, 64 I/O Reg & 160 Ext I/O Reg Loca

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Hi,

While I'm reading the datasheet (page 16 & 17), Address 0x0000~0x00FF belongs to the above registers. And since SRAM is 512B (0x00100~0x02FF), then where are these registers physically residing on the chip? A bit confused :?

Once an engineer, forever an engineer

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In the lower right hand corner of the chip......
Seriously, not sure what your confused about, the registers/io ports are located at the lower ram addresses, and general read/write memory above that.
JC

Last Edited: Fri. Jun 7, 2013 - 01:15 PM
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Quote:

then where are these registers physically residing on the chip?

I don't quite understand the question. Does it matter if they are in the lower-left corner, or the upper right corner?

If I had to guess, they'd be near the logic for their respective peripheral subsystems, reacting to the events on one side and address selection/read-write operations from the other. The datasheet block diagram kind of hints at that. Also explore all the signals on e.g Figure n-m. General Digital I/O.

There is a site where microcontrollers and other chips are etched away and an AVR was done there. Perhaps someone will remember the site.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Look at:

Quote:
Table 3-1. Memory Mapping.

I bet there are gaps in the "160" Ext I/O addresses, but I have no desire to look.

All modern AVRs follow this basic pattern. In practice, a C programmer does not need to worry about 'short IN/OUT' addresses (0x20-0x5F) or 'long EXT' addresses (0x60-0xFF). Most ASM programmers will use the LOAD and STORE macros.

Yes, it does make a massive difference to access time and most importantly atomicity.

You can see the answer for physical address location from the data sheet.

David.

Last Edited: Fri. Jun 7, 2013 - 01:22 PM
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I found the site--Flylogic. The Mega88 teardown might be of interest, with the annotated picture near the bottom. It doesn't have I/I registers demarked, though.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Sorry, should have been clearer in my question. In figure 3-2, these registers were mentioned above the SRAM but I guess it was just showing the addressing & not part of SRAM.

Anyway, thanks for the replies. I'm starting out with these AVR uC & they are getting very interesting.

Once an engineer, forever an engineer

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Quote:

but I guess it was just showing the addressing & not part of SRAM.

You are right it's showing CPU addressing of everything that can be accessed using LD/ST. SRAM is just one of the blocks in that "map" - from 0x100 to ISRAM_end (0x2FF).

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clawson wrote:
You are right it's showing CPU addressing of everything that can be accessed using LD/ST. SRAM is just one of the blocks in that "map" - from 0x100 to ISRAM_end (0x2FF).

Thanks.

Once an engineer, forever an engineer