ATTiny44A reading bandgap with Vcc as ref

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When reading the 1V1 bandgap using Vcc as vref, I find that I need to add a fairly long delay after setting the MUX register for internal 1V1 bandgap.
I have come across this before, but simply sledgehammered it by reading the 1V1 20 times and using the last reading, but I'd like to understand what's happening.
The ATTiny44a datasheet says:
"Internal voltage reference options may not be used if an external voltage is being applied to the
AREF pin."
Does this mean that I should really have a cap on the AREF pin just to be able to read the bandgap? If so, that's a major PITA, as I was hoping to use that pin!
It certainly doesn't look as though the bandgap is connected to AREF on the schematic, but I guess it is more of a block diagram...

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Is this the >>only<< setup for the ADC? ( (A)Vcc as VREF)

There were some threads a while back that indicated there is some "effort" (i.e. a bunch of conversions) needed to "bleed down" the reference from Vcc level to bandgap level. I didn't think there would be problems going the other way...

Hmmm--perhaps the sample-and-hold cap has a high level, and many conversions needed to bleed it down? Try a reading on a grounded pin first; then the BG. Or read the GND channel first, then the BG. Same results?

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Quote:

I find that I need to add a fairly long delay after setting the MUX register for internal 1V1 bandgap.

Didja see this note on the ADMUX table:
Quote:
2. After switching to internal voltage reference the ADC requires a settling time of 1ms before measurements are stable. Conversions starting before this may not be reliable. The ADC must be enabled during the settling time.

Given the location of the note, I'd assume it means the BG >>channel<< selection and not the use of BG as ref.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I will try reading the GND channel first, I have done this before, for similar reasons.

It seems strange to me that the internal bandgap should have a high impedance, as I'm sure the datasheet mentions an amplifier.

Four legs good, two legs bad, three legs stable.

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OK, if I read GND first, then switch the MUX to bandgap, I get a reading of 92(decimal).
If I simply read the bandgap(with no addtitional delay after setting MUX) I get a value of 919.
The value I'm after, and that will appear if I read bandgap 20 times, or add a substantial delay(don't ask how long, I'd have to turn off optimization to get readable asm code) is around 350.
This seems to indicated that the bandgap reference has a very high source impedance, which seems strange to me as it's designed to be used as a reference. Maybe the ADC input comes from before the amplifier?

I may see if I can bodge a cap onto AREF tomorrow, as I can probably do without that pin.

Four legs good, two legs bad, three legs stable.

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Quote:

or add a substantial delay(don't ask how long, I'd have to turn off optimization to get readable asm code)

Well, the datasheet says 1ms. A conversion at 50kHz ADC clock takes about 250us; a conversion at 200kHz clock takes about 65us. So if you found that you need about 20 reads that would indeed be about 1ms if your ADC clock is about 200kHz.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Where did you find the 1mS figure? My datasheet says 70uS max(but I know I have seen a 1mS figure somewhere today - could have been the non A part datasheet).

Four legs good, two legs bad, three legs stable.

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OK, found it.
"2. After switching to internal voltage reference the ADC requires a settling time of 1ms before
measurements are stable. Conversions starting before this may not be reliable. The ADC must
be enabled during the settling time."
I read that, and found it very confusing, as I'm not switching to internal voltage reference, I'm merely trying to measure it. I suppose that means that the chip is clever enough to know that is has to turn on the bandgap so that I can read it, but it is at variance with the 40uS typical 70uS max quoted elsewhere.
I will add a 1mS delay.

Still not entirely sure about being able to use AREF as a digital input, though. I will experiment tomorrow.
Have to go to the pub quiz now...

John

Four legs good, two legs bad, three legs stable.

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Quote:

Where did you find the 1mS figure?

LOL--didn't I say above...
Quote:

Didja see this note on the ADMUX table:
Quote:
2. After switching to internal voltage...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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This may be of interest, John: https://www.avrfreaks.net/index.p...

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theusch wrote:
Quote:

Where did you find the 1mS figure?

LOL--didn't I say above...
Quote:

Didja see this note on the ADMUX table:
Quote:
2. After switching to internal voltage...

No, I didn't see that, as you posted it while I was typing my post.
However, as I have now said, I found that rather confusing, as I am not ever switching reference. I do all the ADC readings with vcc as the reference.

I take your point about where the note was, but I am old enough that I sometimes suspect lazy copy-and-paste stuff in datasheets.

Anyhow, it would seem that a 1mS delay is the order of the day.

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One last time. Does anyone think that I should avoid using the AREF pin and hang a cap on it
?(see much earlier post, with quote from datasheet).

Quote:
Internal voltage reference options may not be used if an external voltage is being applied to the
AREF pin.

Four legs good, two legs bad, three legs stable.

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There must always be a cap on AREF pin.
Experimenting without it is a time wasting (in my opinion).

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Visovian wrote:
There must always be a cap on AREF pin.
Experimenting without it is a time wasting (in my opinion).

Not according to the datasheet. Since I am only ever using Vcc as the analog reference, the AREF pin is disconnected from AREF.
Which brings me back to my earlier question, namely. will the 1V1 bandgap be connected to AREF if I select it as the ADC input(NOT REFERENCE, INPUT)?
I don't think so, but I guess I will have to measure select bandgap as input and measure the pin.

Attachment(s): 

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I have now measure the AREF pin whilst the bandgap is selected as the input channel and Vcc is selected as the reference. The voltage shown is around 3V3, which I would expect, as the pin is connected via a 10K resistor to another device. If the internal bandgap was using the AREF pin then I think I'd see a lower reading, especially as I know what the ADC result is.

So, to sum up, I found that 1mS was not quite enough, so I settled on 2mS delay after setting the MUX for bandgap as input.
I still don't understand why this delay is needed, the extract from the datasheet quoted by The Usch explicitly talks about "switching to internal voltage reference", I'm not doing that, I'm only ever using Vcc as the ref.

The AREF pin does not seem to be relevant at all(remember that I am always using Vcc as the reference).

Anyway, it works now and I haven't lost the use of the AREF/PA0 pin.
Thanks to all who posted.

John

Four legs good, two legs bad, three legs stable.

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The bandgap as input need several readings until you get the right value:

https://www.avrfreaks.net/index.p...

Peter

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danni wrote:
The bandgap as input need several readings until you get the right value:

https://www.avrfreaks.net/index.p...

Peter

Yep, already discovered that. You are a bit late to this particular party.
Thanks for posting the link, though, I did search the forum yesterday, but obviously didn't go back far enough in time.
I am happy with my 2mS delay for now, especially as I will only be making this measurement about once every 5 minutes.

John

Four legs good, two legs bad, three legs stable.