Attiny24A. Startup delay. How long is one CK?

Go To Last Post
15 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I need to find out how long one CK is. I can't find the information in the complete datasheet.

 

According to the picture below the CK is generated by an internal clock generator. I can't find any more information about this.

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

What is your external clock frequency?

 

David

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

It will be 8 MHz.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

CK would be the period of what ever your chosen clock source might be.

David (aka frog_jr)

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Could the "clock generator" be similar to the "watchdog oscillator". The watchdog oscillator looks like it could be an RC-oscillator of some sort.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

frog_jr wrote:

CK would be the period of what ever your chosen clock source might be.

 

Where can I read this statement? In the second picture in my posting the clock generator module is drawn as a block with no clock input. So I think it is internally generated :-/

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I am not certain what device you are using; however, (for example) the AT90USB64/128 (AT90USB1286) datasheet of 11/09 shows:

6.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.

 

Edit: I'm blind! Missed the ATtiny24A in the title.blush

Edit2: Although the text is the same in the ATtiny24A datasheet of 06/12 (Section 6.2).

David (aka frog_jr)

Last Edited: Mon. Mar 26, 2018 - 03:32 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

"CK" represents the period of the system clock. The block diagram is slightly misleading (not a new thing). You are correct that it shows no external inputs but note that the CKSEL bits are applied to that block. The answer is "period of the system clock" and take the block  diagram as "part, but not all, of the truth".

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ka7ehk wrote:

"CK" represents the period of the system clock. The block diagram is slightly misleading (not a new thing). You are correct that it shows no external inputs but note that the CKSEL bits are applied to that block. The answer is "period of the system clock" and take the block  diagram as "part, but not all, of the truth".

 

Jim

 

So if I use en 8 MHz external oscillator that is divided internally by 8 then fCK is 1MHz? And if I use en 8 MHz external oscillator that is divided internally by 1 then fCK is 8MHz? 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

9.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock
from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
 

Why would you think that CK is  >>not<< the frequency your AVR is running at?

 

If you tell why it matters, we might have more pertinent experience, and more interest.

 

Several peripheral subsystems also use CK in their description, including ADC and SPI.  We all know from experience that the CK for those subsystems is the system clock which then might be divided.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

MASIP is correct in the conclusion:

 

So if I use en 8 MHz external oscillator that is divided internally by 8 then fCK is 1MHz? And if I use en 8 MHz external oscillator that is divided internally by 1 then fCK is 8MHz? 

Beware, however: If you choose fuses for "External Clock", it expects a stand-alone, powered clock source with a single output (see Figure 6.2). This is quite different from "Crystal Oscillator/Ceramic Resonator" (see Figure 6.3). SUT 1:0 value of "00", which you circled, COULD apply to "External Oscillator, to internal 128KHz Oscillator, or to "Crystal Oscillator/Ceramic Resonator". According to table 6.9, SUT 1:0 value of 00 when applied to Crystal Oscillator sets it up for a crystal or resonator 0.9MHz or less. Your declared 8MHz would have SUT 1:0 bits of 11. Table 6.3 ONLY APPLIES TO EXTERNAL OSCILLATOR, not to a crystal!

 

As a side note, since this is an EXTERNAL OSCILLATOR, it does not turn off during sleep. Thus, when it wakes up, the oscillator is already running, and the startup time is very fast. This also means that the power consumption does not drop to such a low level, because the oscillator is still running.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Mar 26, 2018 - 04:29 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ka7ehk wrote:

MASIP is correct in the conclusion:

 

So if I use en 8 MHz external oscillator that is divided internally by 8 then fCK is 1MHz? And if I use en 8 MHz external oscillator that is divided internally by 1 then fCK is 8MHz? 

Beware, however: If you choose fuses for "External Clock", it expects a stand-alone, powered clock source with a single output (see Figure 6.2). This is quite different from "Crystal Oscillator/Ceramic Resonator" (see Figure 6.3). SUT 1:0 value of "00", which you circled, COULD apply to "External Oscillator, to internal 128KHz Oscillator, or to "Crystal Oscillator/Ceramic Resonator". According to table 6.9, SUT 1:0 value of 00 when applied to Crystal Oscillator sets it up for a crystal or resonator 0.9MHz or less. Your declared 8MHz would have SUT 1:0 bits of 11. Table 6.3 ONLY APPLIES TO EXTERNAL OSCILLATOR, not to a crystal!

 

As a side note, since this is an EXTERNAL OSCILLATOR, it does not turn off during sleep. Thus, when it wakes up, the oscillator is already running, and the startup time is very fast. This also means that the power consumption does not drop to such a low level, because the oscillator is still running.

 

Jim

 

Yes, I'm planning to use an external oscillator, not a crystal oscillator/ceramic resonator :-)

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Then you are looking at the correct section.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Unfortunately, at least for ATtiny*5, CK is not the clock but the divided clock!! I checked this with my oscilloscope. The datasheet should note this but currently it doesn't.

 

Therefore, clock divider setting has large impact to reset and wakeup time from powerdown. For best power save, the clock division ratio should be set to 1:1 before entering a powerdown sleep. For reset, the clkdiv8 fuse applies and should be cleared for minimum startup time. Otherwise, oscillator startup consumes additional power. This would be noticeable in a low-power application where watchdog timer (9 µA) periodically wakes the CPU to do additional things, as checking an analog input with its A/D converter (some 100 µA). Note that disabling the ADC before entering PowerDown sleep is important, even when no conversion will take place, i.e. the last conversion has been done. Otherwise, the ADC consumes extra power. (I have not checked to use the PRR register instead.) This is documented but weird.

 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Henrik Haftmann wrote:
Therefore, clock divider setting has large impact to reset and wakeup time from powerdown.

perhaps you think down a different path, but to me that would be my first assumption.

Henrik Haftmann wrote:
For best power save, the clock division ratio should be set to 1:1 before entering a powerdown sleep.

Now I have more questions...are you talking about PowerSave sleep, or PowerDown?

 

In either case, I'd agree that it may take longer to wake up with a slower CK.  But why is it "best power save"?  How does the AVR use less power with a faster CK, when the main clock is stopped?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.