I have a conundrum to verify. I've three comparator signals; one is for reset, one for over-voltage and one for under-voltage.
If over-voltage = 1 in LUT0 it sets the CCL sequential gate (RS) as high.
If under-voltage = 0 AND a reset falling edge is detected it sets LUT1 high and the RS becomes low.
The potential issue is while a LUT has an edge detector it's not on each input but on the combined logic, so the RS could be cleared at the wrong time (timing is critical, it must be on the reset edge). Thus I don't believe I can use the LUT edge detect.
The same reset signal is being piped into TMRB0 which I'm measuring in frequency mode (with edge detection set to the falling edge). I've found TMRB can be piped into LUT thereby replacing the direct comparator signal, and since it should fire an event at nigh on the same time
I think it'll do what I'm after. My question is whether the event will fire if I don't have the requisite TMRB interrupt enabled (i.e once the interrupt flag is set) and whether it'll repeatedly fire if the flag isn't cleared?
I should mention the signal is no more than about 200Hz, so if necessary I could easily clear the interrupt flag for TMRB in software to allow the next event to fire - but I'd rather keep the whole approach to a 100% hardware based solution if possible.