ATTiny 85 ADC read timing

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#1
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I am using the following subroutine to read the ADC input. Just enabling the ADC function then looping through this subroutine over and over shows me, on my scope, that NU2, pin 3 of the ATTiny, goes high for .9 ms. It takes the ADC that long to complete a single read. Really? That's pretty slow. I am using the internal RC oscillator set at 8 MHz and the divide by function on the clock. How can I speed the ADC read time up without adding an external crystal? I am watching a string of pulses that are clocking at about 4KHz and the ADC takes 1.111KHz to complete a single read.

;
;===================================
;READ THE ADC 
;RESULTS ARE AUTOMATICALLY STORED
;IN ADCH AND ADCL REGISTERS
;===================================
;
;
READ_ADC:
	sbi portb, NU2			;turn on "ADC running" pulse on pin 3 of MCU
	sbi ADCSRA, ADSC  		;start conversion ADSC to 1 (zeros when done)
loopX:   
	sbic ADCSRA, ADSC  		;ADSC bit goes low when conversion complete
 	rjmp loopX         		;not complete, keep checking
	cbi portb, NU2			;turn off "ADC running" pulse on pin 3 of MCU
	ret
;
;

BADBAUD

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You measure frequency in Hz.
You measure period (time) in microseconds.

Your data sheet tells you the number of ADC_cycles for the ADC to complete. The ADC_cycle depends on the ADPSx (prescaler) bits. At 8MHz you need to prescale since the ADC is only guaranteed to manage 65us conversion time. e.g. 15000 conversions a second.

You can run on the 8MHz RC oscillator. Either remove the CKDIV8 fuse or use the CLKPR register. Note that you should do the CLKPR changes within 4 cycles. This is no problem for ASM.

David.

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This is what I have as ADC enable. Should I lower the prescaller number?

;
;================================
;    ENABLE THE ADC PROCESS
;================================
;
;
ENABADC:
	ldi TEMP, 0b00000011	;select ADC3 on PB3 as single ended ADC input
	out ADMUX, TEMP
	ldi TEMP, 0b10000110	;ADC enabled and prescaller is 64
	out ADCSRA, TEMP
	ldi TEMP, 0b00001000	;disable digital input on ADC pin
	out DIDR0, TEMP
;
;

BADBAUD

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First off, you read up on how to set the CLKPR register so you know what speed your AVR is clocked at.

Then you see how many clock cycles are needed at 8MHz to get 65us. i.e. 65 x 8 = 520
If you use a ADPS of 32 the conversion is 54us.
An ADPS of 64 is 108us.

In practice, I bet both values would work.

You may find it helpful to use the symbolic names in your code. It is less long-winded than the English comment. All the same, you have written your statements with the explanatory comments. An excellent style !!

So I think it comes down to you reading Chapter 6. System Clock and Clock Options

David.