ATtin84A INT0 sense control problem

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According to page 50 of the datasheet Table 9-2, there are four combinations of ISC01 and ISC00 that affect how the INT0 interrupt fires.  I was unable to get rising edge interrupt sense control.  I eventually changed my circuit design to accommodate falling edge, but I'm still curious why setting these bits apparently had no effect  I tried ISC01:ISC00 = 0b11 and 0b01 but neither worked.  In fact, no code at all seems to cause falling edge sensing:

ISR(EXT_INT0_vect)
{
	// Turn off sleep enable.
	MCUCR &= ~(1 << SE);
	
	// Sound the alarm!
	while(1)
	{
		PORTA ^= (1 << PIN_ALARM);
		_delay_ms(50);
		PORTA ^= (1 << PIN_ALARM);
		_delay_ms(100);
	}
}

int main(void)
{
	DDRA |= ( 1 << PIN_ALARM );	// Set up alarm output pin.
	DDRB &= ~( 1 << PORTB2);	// Make INT0 pin an input.
	PORTB |= ( 1 << PORTB2);	// Enable pull-up on INT0 pin.
	GIMSK |= (1 << INT0);		// Enable external interrupt for INT0. (p.50)
	sei();						// Enable interrupts.
	blink_alive();				// Blink for a bit to show main() is running.
	MCUCR |= (1 << SM1);		// Select power-down mode. (p. 37)
	MCUCR |= (1 << SE);			// Enable sleep when 'sleep' instruction is issued. (p. 36)
	sleep_cpu();				// Off to sleep now...	

Of course, when trying for rising edge, I did not set the pullup just set it to input.

 

The code above results in INT0 ISR being fired when the PB2 is grounded.  But for the life of me I can't figure out why.  Any advice how, or in what order, to set MCUCR:ISC01 and MCUCR:ISC00 to get desired, predictable operation on the rising edge?  Thank you for taking a look.

This topic has a solution.
Last Edited: Tue. Nov 22, 2016 - 04:08 AM
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I didn't think edge sensitive ints worked in sleep.

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jhelmick wrote:
Of course, when trying for rising edge, I did not set the pullup just set it to input.

???  So, you let it float? You are driving the pin both ways?  But you do >>not<< drive the pin both ways when you configure for falling edge?

 

[indeed, double-check the datasheet for your AVR model w.r.t. deep sleep and level-triggered external interrupt and cascading interrupts]

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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It would help to see the schematic of your int sources.  If they are buttons, there have been many threads on using buttons for wake up. 

 

 

(Possum Lodge oath) Quando omni flunkus, moritati.

"I thought growing old would take longer"

 

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ki0bk wrote:
If they are buttons, there have been many threads on using buttons for wake up.

...especially on "modern" AVR8 devices with pin-change.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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It is a configurable SPDT switch of my own design.  But I might see if I can find the threads you're talking about, as mechanical switches share many common properties.

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Ah, you are correct!  The footnote on p. 33 of the datasheet refers to power-down mode, only level interrupt supported.  That explains it completely.  Thank you, I should have read the footnote.

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jhelmick wrote:
Thank you, I should have read the footnote.

And/or the paragraph on power-down:

 

8.4 Power-down Mode
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out
Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This
sleep mode halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. See ”External Interrupts” on page 52for
details

 

And/or 11. External Interrupts:

 

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held
low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an
I/O clock, described in ”Clock Systems and their Distribution” on page 26. Low level interrupt on
INT0
is detected asynchronously. This implies that this interrupt can be used for waking the part
also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except
Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. ...

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.