ATSAME70Q21 Dual Serial 2-Wire within QSPI

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G'day,

 

I'm looking to interface 2 16-bit 16 channel 1Msps ADCs with an ATSAME70Q21 and am having some issues determining how best to design their interface. Each ADC has both a 16-bit parallel interface, which given the single 8-bit parallel interface of the ATSAME won't be an ideal option, and a serial interface. The serial interface requires two data lines for use at full throughput (1Msps), but can operate at reduced throughput on a standard single data line SPI. The QSPI of the ATSAME would be perfect for one of the ADCs as the QSPI can be configured for dual SPI mode, however it would still leave the second ADC without a full throughput interface option.

 

Here's what I'm thinking. If I designed the layout carefully, I could share the QSPI clock between both ADCs. Then I could connect 2 of the QSPI data lines to ADC1 and the other 2 data lines to ADC2 and effectively use the QSPI in full quad SPI mode, then perform the required data rearranging in post processing.

Is this possible/plausible/crazy? I looked at using 16-bit parallel-in/serial-out shift registers as an alternate solution but they were quite expensive and would likely run into the same throughput issue as using one wire SPI.

 

Any input, recommendations, alternatives, etc. would be greatly appreciated!

Last Edited: Sun. Apr 28, 2019 - 10:32 PM
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I've done a little more reading into this option. Each of the ADCs actually has 3 data lines, 2 outputs (which carry the conversion data) and one input (which carries register read requests and register writes). As such, for the above approach to work, the 4 QSPI lines would need to be for ADC data output only, with 2 of the available additional SPI interfaces on the MCU used solely for each of the input ADC data lines. In my mind this seems to work out, as the QSPI and regular SPI interfaces on the ATSAME MCU have configurable clocks derived from the same peripheral clock, so as long as the applied clock division (divided from the peripheral clock) is common across QSPI, SPI1 and SPI2, the 4 ADC output data lines and 2 ADC input data lines should all be synchronised as required?

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Sam7 isn’t arm7!

Is this still shock dyno? You seem tospend a lot of time doing bizarre workarounds rather than just doing the simplest and obvious.

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I ended up coming to that very conclusion Kartman, I'm just going to stick with regular SPI and see how I go.