I'm looking to interface 2 16-bit 16 channel 1Msps ADCs with an ATSAME70Q21 and am having some issues determining how best to design their interface. Each ADC has both a 16-bit parallel interface, which given the single 8-bit parallel interface of the ATSAME won't be an ideal option, and a serial interface. The serial interface requires two data lines for use at full throughput (1Msps), but can operate at reduced throughput on a standard single data line SPI. The QSPI of the ATSAME would be perfect for one of the ADCs as the QSPI can be configured for dual SPI mode, however it would still leave the second ADC without a full throughput interface option.
Here's what I'm thinking. If I designed the layout carefully, I could share the QSPI clock between both ADCs. Then I could connect 2 of the QSPI data lines to ADC1 and the other 2 data lines to ADC2 and effectively use the QSPI in full quad SPI mode, then perform the required data rearranging in post processing.
Is this possible/plausible/crazy? I looked at using 16-bit parallel-in/serial-out shift registers as an alternate solution but they were quite expensive and would likely run into the same throughput issue as using one wire SPI.
Any input, recommendations, alternatives, etc. would be greatly appreciated!