ATMEL ICE SPI Electrical Characteristics

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I'm trying to find the DC characteristics for the SPI output lines SCK and MOSI.  For example, Voh and Vol at some source and sink currents.

 

Does anyone have a link to this info?

 

Thanks!

 

 

 

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On the Mega328 datasheet, page 310 there are the Typical I/O drive levels that I would think also apply to the SPI pins as they are nothing more than General Purpose I/O that are simply connected to a clock driver, and shift register.

 

Jim

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Would agree with East Coast Jim. On AVR Tiny/Mega, they appear to be standard I/O pins. Typically, the  only ones that are not are reset and crystal pins (and analog input pins that do not have an alternate digital function).

 

West Coast Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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davethomaspilot wrote:
Does anyone have a link to this info?
I don't

The sink currents are likely as is in the UC3A4 datasheet.

The source currents are iffy due to the level conversion (pass FET with active pull-up?), series termination, and protection.

 


Atmel-ICE

Architecture Description

http://www.atmel.com/webdoc/GUID-DDB0017E-84E3-4E77-AAE9-7AC4290E5E8B/index.html?GUID-9B532A87-65FB-47FB-9572-A406F9A71F46

Atmel-ICE

Main Board

http://www.atmel.com/webdoc/GUID-DDB0017E-84E3-4E77-AAE9-7AC4290E5E8B/index.html?GUID-11CB875B-461E-4F25-A26B-5CCD1D06BDCE

...

At the heart of the Atmel-ICE main board is the Atmel AVR UC3 microcontroller AT32UC3A4256, ...

...

http://www.atmel.com/devices/AT32UC3A4256.aspx

 

"Dare to be naïve." - Buckminster Fuller

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Why are the drive levels of a 328P relevant? 

 

I was asking about what the Atmel ICE could drive.  Were you thinking that's what is driving the SPI in the Atmel ICE?

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Given there aren't any specs on the SPI drive capability, I'm thinking it wouldn't be good to count on resistor isolation between processors that are on a bus that uses either SCK or MOSI.

 

In this application, those signals aren't being used for SPI communication between processor.  Just GPIO.  But, I'd like to be able to individually, ISP program each processors in a set of 12 that share SCK and MOSI signals without having to pull the RST line on all processors not being programmed.

 

 

 

 

Last Edited: Tue. Jan 24, 2017 - 07:09 PM
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davethomaspilot wrote:
In this application, those signals aren't being used for SPI communication between processor. Just GPIO. But, I'd like to be able to individually, ISP program each processors in a set of 12 that share SCK and MOSI signals without having to pull the RST line on all processors not being programmed.

Maybe I'm a little new in the SPI area, but if all the processors share the same SPI, how else do you determine which device gets programmed or trashing the lines by multiple devices trying to respond?

 

Isn't the whole point that only a single device is held in reset and slave selected? The Atmel ICE only has a single reset and SS line. Wouldn't you need to have a way of selecting which device gets priority to the ICE?

 

What are you trying to actually accomplish here?

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The processors share signals (now actually only 1, MOSI) but those signals are not used for SPI communication between the processors.

 

While the signal is on the MOSI pin, let's call it SYNC/MOSI.  It's driven by one processor and is an input on the others.  It just happens to be on the same pin that's needed for ISP programming.

 

I would like to program one processor at a time without having to unplug cables between them.  If there are no resistors between the SYNC/MOSI on the shared bus and the local, on card version of that signal, the one processor that is driving SYNC/MOSI would prevent reliable programming of any processor, since there would be contention between the ISP programmer and that processor

 

ISP programming won't occur unless RST is held active.   So, if the programmer can drive one side of a resistor between the on card MOSI signal (for example) to good levels, then its possible to have reliable ISP programming.  The ISP programmer just drives SYNC/MOSI to good levels even though one processor keeps driving the other side of the resistor.

 

Of course I can use jumpers to disconnect SYNC/MOSI from the processor that's driving it to program the "SLAVE" processors.  Or, have a jumper to hold the MASTER in reset during programming.  Both of these techniques will work.

 

But, in this application I have a resistor footprint on each card anyway, so that when it's configured to drive the MOSI/SYNC signal I can impedance match to the 4' wire it's driving.  Speed isn't an issue, so I could make the resistor bigger than needed to prevent overshoot or ringing just to satisfy a programmers drive capability.  But, there's no electrical spec for the ATmel ICE.

 

Not a big deal--many ways to skin the cat.

 

 

 

 

Last Edited: Thu. Jan 26, 2017 - 09:38 PM