ATmega328P WDT period changes with sleep mode

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As here, a system with an ATmega328P using sleep modes, with a regular watchdog wakeup (for a timing 'tick').

 

The WD is used just for its interrupt - not for resetting.

 

But I find that the WDT period changes depending on whether I use Standby or Power Down sleep mode:

 

Standby current consumption:

The peaks are the (brief) wakeups on the WDT interrupts; the wakeup period is ~ 35ms

 

 

Power Down:

The wakeup period is ~ 41ms

 

The Datasheet says the WDT is a separate oscillator, and I can't see any mention of any dependence on or relation to the sleep mode - so why should the WDT change its period in the different sleep modes?

 

I have 4 boards, and they all have similar behaviour.

 

The AVR has an external crystal; the key difference between Standby and Power Down (AFAIKS) is that the oscillator stays running in Standby, but stops in Power Down; but why should that make any difference to the WDT - which is a separate oscillator?

 

(the current consumption traces are from the Microchip Data Visualiser, using the measurement module on a SAML21 Xplained-Pro)

 

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Last Edited: Thu. Oct 21, 2021 - 02:23 PM
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The WDT oscillator is an R/C osc, perhaps its sensitive to supply voltage variations, but I would not think that much....

Jim

 

 

FF = PI > S.E.T

 

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ki0bk wrote:
perhaps its sensitive to supply voltage variations

Indeed it is:

 

 

 

 

Quote:
 but I would not think that much....

Quite so - and why would the supply change when changing the Sleep mode?

 

The current measurements are all at 3V3

 

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Last Edited: Thu. Oct 21, 2021 - 04:37 PM
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There are short peaks on both sleeps, what is it, please.

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just noise

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Those reaching 90% of max active current- can not be a noise. One on first, two peaks on second picture.

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I added a GPIO toggle in the WD ISR - so I can see when the interrupts happen both when asleep & awake.

 

In the Power Down case, the WD interval does go back to ~ 35ms  when awake - so it appears that the interval is stretched just in PD mode.

 

 

so does this "internal reset" stop the WD?  That could explain why the WD period is "stretched" when using Power Down ... ?

 

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awneil wrote:
That could explain why the WD period is "stretched" when using Power Down ... ?

Forehead slap!   Duh! 

 

FF = PI > S.E.T