Atmega328P datasheet - SET definition ?

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In the Datasheet for the 8 bit AVR Microcontrollers  ATmega328/P , page 148 it is written:  

Bit 0 – TOV: Timer/Counter0, Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one
to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set,
the Timer/Counter0 Overflow interrupt is executed.

 I always thought that SETting a bit meant to make it a  "1" 

In the datasheet it is clearly indicated that "TOV0 is cleared by writing a logic 1" to the bit.

What's the catch ?    SETting a bit is 0 or 1 ?

If I define TIFR0 ( the actual register ) equal to 1, isn't the first bit of that variable SET ?

 

Please, un-confuse me someone .

 

This topic has a solution.
Last Edited: Tue. Sep 14, 2021 - 11:49 PM
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FredCailloux wrote:
 I always thought that SETting a bit meant to make it a  "1"

This is correct and means setting the bit to 1.

 

But what you see in the datasheet is one-off case where it is the opposite. Writing 1 to that bit would actually set it to 0. This is why it is mentioned in quote marks "cleared by writing logic 1". 

 

If you try to clear TOV0 by writing 0 to that bit, it will not happen.

“Everyone knows that debugging is twice as hard as writing a program in the first place. So if you're as clever as you can be when you write it, how will you ever debug it?” - Brian W. Kernighan

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This is a feature of many interrupt flag register bits.

Some hardware action sets the bit (makes it "1") and normally some other hardware action (in this case execution of the associated ISR) clears the bit (makes it a "0").

However, sometimes it is useful to clear a bit when the interrupt is not enabled. In this case writing a "1" to the bit will clear it.

In the case of the TIFR0 register, there are three bits (OCF0B, OCF0A and TOV0) and if you want to clear a specific bit you can do so (without disturbing the other bits) by:

    TIFR0 = (1 << TOV0);     // clear TOV0 bit

 

Edit: changed from "magic number" (0x01) to (1 << TOV0)

David

Last Edited: Sun. Sep 12, 2021 - 09:19 PM
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This is a feature of many interrupt flag register bits.

And not just Atmel chips, it was the case with Motorola chips about 30 years ago.

John Samperi

Ampertronics Pty. Ltd.

https://www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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You are not performing memory operations, but rather memory-mapped I/O.   The CPU has 8 data bits and a R/W line to the peripheral.   The peripheral can choose to use the R/W line in ways that are not analogous to memory operations.   So if you write a one to one of the bits the peripheral may then return a "0" when you do a read.  I hope this helps.

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Even in responses, above, "set" is used ambiguously:

 

Writing 1 to that bit would actually set it to 0.

Correctly, we should probably write "clear it to 0". But, that ambiguous usage is so common that many just shrug their shoulders, effectively saying "well, I know what was meant". That applies to the original question, also. 

 

In the case of interrupt flags, it helps to distinguish between the action (writing one to force a clear operation) and the result (clearing a bit). It is NOT that the bit written is copied to the register location. It causes an action to take place, like resetting a counter.

 

Jim 

 

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Another way to think about this, is to pretend it's similar to the SR Type FlipFlop you learned about in Digital Electronics classes.

 

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N.Winterbottom wrote:
Another way to think about this, is to pretend it's similar to the SR Type FlipFlop you learned about in Digital Electronics classes.

Above a "1" sent to the "Set" input causes the Q output to become "1", while a "1" sent to the "Reset" input causes the "Q" output to be cleared to "0".

This is how flag registers work.....     when you read a flag register, you see all the Q outputs, when writing to the flag register, your talking to the Reset inputs.

when the "condition" occurs internally, it writes 1 to the Set input. 

 

Jim

 

 

Keys to wealth:

Invest for cash flow, not capital gains!

Wealth is attracted, not chased! 

Income is proportional to how many you serve!

 

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As MattRW said, the key thing to remember is that this is not just memory - this is hardware IO.

 

It is common to have registers where writing a '1' to the register will cause some associated hardware flag to be set/reset/toggled; eg, see:

 

see: https://www.avrfreaks.net/commen...

and: https://www.avrfreaks.net/commen...

and: https://www.avrfreaks.net/commen... - illustrated

 

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OK, I get the above explanations. However, still some confusions remain. 

The bit TOV0 is SET when an overflow occur in Timer/Counter 0

That TOV0 bit goes to 1 when it gets SET ? Or does it go to 0 ? 

If it is SET to 1 why would poking a 1 to that same bit would it reSET it to 0 (or 1 ) 

This is getting really mind boggling.

when the datasheet mention SET in that phrase above, does that mean it goes to 0 or 1 ? 

 

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SET always means a 1.

If it is SET to 1 why would poking a 1 to that same bit would it reSET it to 0 (or 1 ) 

You may NOT be necessarily writing to the same bit, think of the RS flip flop above. The bit in the write is just a mask and it may internally be doing a completely different operation.

 

ie you are READING the Q OUTPUT which has been SET by the hardware using the SET INPUT of the RS flip flop and when you write to the same place you are writing to the RESET INPUT of the RS flip flop.

 

If you write or read to the USART (or to the SPI ) data register you are talking to 2 different registers even though they appear as being the same.

 

Just surrender to the force and accept it is so cheeky you will live happily thereafter.

John Samperi

Ampertronics Pty. Ltd.

https://www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when

Here the implied contrasting sentences make it clear (pun!!), that they are opposites ( set=1, clear=0)

 

better

bit TOV0 is set to one when an overflow occurs in Timer/Counter0. TOV0 is cleared to zero by hardware when

or maybe

bit TOV0 is set to one when an overflow occurs in Timer/Counter0. TOV0 is set to zero by hardware when

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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FredCailloux wrote:
If it is SET to 1 why would poking a 1 to that same bit would it reSET it to 0 (or 1 ) 

Go back and re-read #5 and #9.

 

Again, the key thing to remember is that this is not just memory: so you are not "poking a 1" to that same bit - you are writing a 1 to a register, and that action causes the flag to be cleared.

 

You are not writing directly to the flag.

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Quote:
The bit TOV0 is set when an overflow occurs in Timer/Counter0.
This bit of the text means that the bit that you read from the status register will be 1 after an overflow even has occurred.

TOV0 is cleared by hardware when executing the corresponding interrupt handling vector.

This means that IF you have also set the interrupt enable and provided an ISR for the the event then as the CPU is interrupted and vectors to the handling ISR the state of the bit in the status register will be changed from 1 to 0.

Alternatively, TOV0 is cleared by writing a logic one to the flag. 

Rather than enable and provide an ISR you can just use the status bit in "polled mode" so you would have something like:

void delay() {
    TCCR0B |= (1 << CS00);          // start timer
    while (!(TIFR0 & (1 << TOV0))); // wait for overflow event
}

here the TOV0 bit in TIFR0 is repeatedly being tested to see if is has made the transition from 0 to 1 to show the overflow has occurred. But if the code were only this then the next time delay() is called the bit is still set form last time so immediately it will fall out of the while() loop and there won't be much of a delay. So the code needs to clear the bit so it's ready for next time. For atomicity this is done by a write of 1 to the flag bit though, as others have said, it's not a memory bit a write has a different action to a read. So:

void delay() {
    TCCR0B |= (1 << CS00);          // start timer
    while (!(TIFR0 & (1 << TOV0))); // wait for overflow event
    TIFR0 = (1 << TOV0);            // clear the flag for next time
}

simply resets the bit.

 

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FredCailloux wrote:
when the datasheet mention SET in that phrase above, does that mean it goes to 0 or 1 ?

OK - Perhaps Fred is a French speaking Canadian and this is a language thing.

In English the word SET is (to use a C++ idiom) grossly overloaded. Google tells me  "set holds strong at 430 definitions, per the 1989 O.E.D".

 

The Datasheet uses SET with this definition:

  • ELECTRONICS

    cause (a binary device) to enter the state representing the numeral 1.

 Another more general definition:

  • verb

put or bring into a specified state.

 

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N.Winterbottom wrote:
Google tells me  "set holds strong at 430 definitions, per the 1989 O.E.D".
I see to remember that it is the most overloaded word in the English language. No other words has as many definitions.

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Jeepers, let's not talk about whether our program will run

 

Run - 396 (definitions)

 

Seems like programming is a perilous endeavor! 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Damn, my origins are now revealed smiley. Yes I am a french speaking Canadian. 

And let me assure you all, I do make the difference between

I will SET an appointment

     and

This program SET bit A .

 

Anyway, I think I'm done with this question. I get it and I am settling for js's answer:

" Just surrender to the force and accept it is so cheeky you will live happily thereafter. "

 

Cheers everyone.