[?] Atmega328P - ALU and multiplier question

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Hi ,

 

I'm studyng the AVR architecture and assembly language...but I'm not sure about ALU operations.

 

1) please , Look at manual :

http://ww1.microchip.com/downloa...

at pag.281 under the "Operation" column,  Does it mean ALU operation ? I think that is the ALU operation but i'm not sure

 

2) and in order to unerstand multiplier I'm reading this one :

http://ww1.microchip.com/downloa...

at pag. 3 When it says

<<

This unit is functionally equivalent to a multiplier directly connected to an Arithmetic Logic Unit (ALU).  ( I searched on forum but still I'm not sure)

>>

I know multiplier is an Shift-and-Add so what it is this unit ?Does exist an hw multiplier or is the ALU makes shift and add? The mul instruction doesn't mean there is a hw multiplier

I'm a bit confused

 

3) I know CPU read opcode from Program memory and store it on two  8 bit registers . ALU read the registers and process the opcode , it's right ?

Does the ALU process every istruction read from program memory?

Thanks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Cirano wrote:
under the "Operation" column,  Does it mean ALU operation

It just describes what the instruction does - it's not a description of how or where it is performed

 

 

 

at pag. 3 When it says

<<

This unit is functionally equivalent to a multiplier directly connected to an Arithmetic Logic Unit (ALU). 

>>

To understand what "This unit" refers to, you need to read that sencence in context:

AVR201 wrote:
The component that makes a dedicated digital signal processor (DSP) specially suitable for signal processing is the Multiply-Accumulate (MAC) unit. This unit is functionally equivalent to a multiplier directly connected to an Arithmetic Logic Unit (ALU).

So "this unit" means "the MAC".

 

 

Does exist an hw multiplier

The whole point of that document is that it describes the Hardware Multiplier!

 

 

 

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My guess is the multiplier is a parallel unit (wallace tree??) rather than a sequential shift/add unit. If it were shift/add, then that would be done via the alu as the control unit would sequence this. This method would be very unRISC though.

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Kartman wrote:
My guess is the multiplier is a parallel unit (wallace tree??) rather than a sequential shift/add unit.

Indeed.

 

Again, the referenced App Note says:

 This multiplier is capable of multiplying two 8-bit numbers, giving a 16-bit result using only two clock cycles.

The "using only two clock cycles" would not seem to suggest  a sequential shift/add unit ?

 

 

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ad 1
Take a look at page 9

ad2

The MUL take 2 registers as parameter, and put the result in registers as the ALU does but it's extra HW so it why they word it that way.

The multiplier is not shift add.

ad3

you are 100% wrong!

The ALU is not involved in opcode reading. (again look at page9)  

 

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wallace tree??

Or perhaps a Dadda multiplier.  Slightly better performance with generally less complexity i.e. gate count and thereby silicon real estate.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

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A bit of parochialism! The germans call the crt a ‘braun tube’. Funnily enough i built a 32x32 multiplier out of four AMD 29516 high speed(for the time!) ‘cray’ multipliers. I couldn’t find a reference to this, so i reverted to what i was learned at skool.

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Cirano wrote:
The mul instruction doesn't mean there is a hw multiplier

Define "hardware".  If your AVR has a MUL instruction, then indeed there are gates, etc. -- hardware -- to carry out the operation.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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The I have to defend OP :)

 

a 68000 and 8086 and ..  Have a MUL instruction but those use the ALU and the time depends on the amount of 1's in one of the operands.

 

the small ARM 0 need to have a MUL instruction but don't need to have a "real" HW multiplier (but I think all have). 

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Hi ,

 

I realized that multplier is hw ( i dont know if it is wallace tree or dadda but it's ok) If it  takes only 2 cycles  is necessarily a mul hardware. Thanks

 

sparrow2 wrote:

The I have to defend OP :)

 

a 68000 and 8086 and ..  Have a MUL instruction but those use the ALU and the time depends on the amount of 1's in one of the operands.

That was my doubt !

 

theusch wrote:

Define "hardware".  If your AVR has a MUL instruction, then indeed there are gates, etc. -- hardware -- to carry out the operation.

True , thanks!

edit:

By hw I mean it use dedicated circuit . I dont know if multiplier hw uses ALU or other circuits

 

 

About ALU question. please look at image :)

 

 

ADD Rd,Rr         0 ≤ d ≤ 31, 0 ≤ r ≤ 31

 

Example code:

.def n1 = r16
.def n2 = r17

	ldi n1,10
	ldi n2,20
	add n1,n2

; Ldi opcode 1110 kkkk dddd kkkk  ( LDI Rd,K)
;        1110 0000 0000 1010 ldi n1,10   -> converted to hex = 0xE00A  k = 0000 1010 and Rd = 0000. R16 start from 0 becouse Ldi range is 16-31. You have a leading 1 -> (1)0000 =16

; Ldi opcode 1110 kkkk dddd kkkk (LDI Rd,K)
;        1110 0001 0001 0100 ldi n2,20  -> converted to hex = 0xE114  k = 0001 0100 and Rd = 0001. R17 start from 1 becouse Ldi range is 16-31. You have a leading 1 -> (1)0001 =17

; Add opcode 0000 11rd dddd rrrr (Add Rd,Rr)
;        0000 1111 0000 0001 add n1,n2  -> converted to hex = 0xF01 d = 10000 (r16) . No leading '1' . Add range starts from zero. r = 1 0001 (r17). No leading '1'

	; Assembled file .hex
	; : 06 0000 00 0AE0 14E1 010F 0B

	; :    -> start line
	; 06   -> data size
	; 0000 -> start address
	; 00   -> record type (data)
	; 0AE0 -> ldi n2,10 ( little endian )
	; 14E1 -> ldi n2,20 ( little endian )
	; 010F -> add n1,n2 ( little endian )
	; 0B   -> checksum

        CU starts to fetch and execute every istruction from Program memory

	add case : add n1,n2 

        When CU decodes 010F ( add n1,n2) what it happens ?
        CU load to registers Rd and Rr the n1 and n2 values and selects by control line the ADD istruction. It asks to ALU to add that value and return the result on Rd (Rd ← Rd + Rr)
I'm not sure , it's right ? Thanks !

sparrow2 wrote:

ad 1
Take a look at page 9

ad3

you are 100% wrong!

The ALU is not involved in opcode reading. (again look at page9)  

 

 

What do you think now  ?

 

especially when I say

When CU decodes 010F ( add n1,n2) what it happens ?
        CU load to registers Rd and Rr the n1 and n2 values and selects by control line the ADD istruction. It asks to ALU to add that value and return the result on Rd (Rd ← Rd + Rr)

 

Thanks !!!!!

Last Edited: Thu. Apr 12, 2018 - 09:48 PM
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i built a 32x32 multiplier out of four AMD 29516 high speed(for the time!) ‘cray’ multipliers

I once made a topographical relief map of a Australia out of bannock bread dough.  So, I guess you win ;-)

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

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"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Mmmmm! Dooooh!

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By hw I mean it use dedicated circuit . I dont know if multiplier hw uses ALU or other circuits

 Other circuits, not that there is any way for you to tell.  There are AVRs that have (presumably) the same ALU but do NOT have the multiplier unit, and they don't have the MUL instructions, either.

I guess it is similar to a co-processor - the multiplier unit is directly activated by an instruction, and has access to some of the same internal buses as the ALU (source operands, in particular), but it isn't actually PART of the ALU (and for example, since it takes 2 cycles, it seems to "lose" access to a destination register, and always uses R0/R1.)  If it were slower, there might have been value in allowing parallel execution in the ALU AND the multiplier at the same time, but for only 2 cycles that probably would have added a lot more complexity than it was worth.

 

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I'm with Lee on this - have they come up with silicon chips that contain something other than transistors then? (yeah, OK, resistive bits and so on - I know).

 

At the end of the day EVERYTHING that happens in a CPU is the result of some transistors switching on and some switching off - so it's all hardware.

 

Is the question here really about the existence of micro-coding ? (but again that's really just a pattern that just dictates the switching order of some other transistors)

 

At the end of the day it's all done in hardware by Vcc level signals being switched on and off.

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What is it you want to do?

 

Is it interest , then I would say you should look at one of the free VHDL or verilog CPU's so you also know how the controlle lines works.

Or is it a school project where you need to explain how a AVR works?

 

Remember that there also is instructions that could use the ALU but probably is done in some extra HW like adder for brace etc.     

 

Often you don't know how a chip works inside, just how the instructions work and how fast.

Like a Z80 only have a 4 bit ALU! but all instructions are 8 or 16 bit! 

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sparrow2 wrote:
Like a Z80 only have a 4 bit ALU! but all instructions are 8 or 16 bit!
Wow in all my years of writing Z80 Asm I never knew that!!

 

(which just proves the point about asm programmers not really needing to know how the opcodes are actually implemented!)

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theusch wrote:
Define "hardware".  

You should ask Atmel Microchip that one - they use the term in their literature as a distinguishing feature of some AVRs ...

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sparrow2 wrote:
look at one of the free VHDL or verilog CPU's

I think the HDL AVRs available are just models - so they don't necessarily replicate exactly how the stuff is implemented in actual AVR chips ... ?

 

As you say:

you don't know how a chip works inside, just how the instructions work and how fast

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just to make it clear I don't mean AVR in VHDL or verilog but a "simple" CPU.

 

I know that there are come FPGA books that describe how to make a CPU.

 

 

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awneil wrote:
replicate exactly how the stuff is implemented in actual AVR chips
As that is the intellectual property ("family jewels") on which a lot of the former Atmel empire was based I doubt anyone is going to supply too much detail about the exact working of AVRs internally.

 

Having said that a lot of these "chip tear down" sites analyse the polysilicon and aluminium pathways to reverse engineer how the chips work internally - so maybe that has been done for the AVR core somewhere?

 

But it's a fair bet that anything in the public domain in Verilog/VHDL purporting to be "AVR core" is almost certainly just a reimplemented, cycle accurate, "work alike" rather than anything based on the original AVR design.

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Yes - that was my point exactly.

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sparrow2 wrote:
I don't mean AVR in VHDL or verilog but a "simple" CPU

Yes, that is the way I read your post - but the OP was asking specifically about the AVR.

 

I know that there are come FPGA books that describe how to make a CPU.

and, indeed, there are open-source CPUs available on the interwebs ...

 

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sparrow2 wrote:

just to make it clear I don't mean AVR in VHDL or verilog but a "simple" CPU.

I know that there are come FPGA books that describe how to make a CPU.

Good idea , I'll try.

 

sparrow2 wrote:

What is it you want to do?

 

Is it interest , then I would say you should look at one of the free VHDL or verilog CPU's so you also know how the controlle lines works.

Or is it a school project where you need to explain how a AVR works?

 

Remember that there also is instructions that could use the ALU but probably is done in some extra HW like adder for brace etc.     

Often you don't know how a chip works inside, just how the instructions work and how fast.

Like a Z80 only have a 4 bit ALU! but all instructions are 8 or 16 bit! 

Understood. I'm too young for College and No school project at moment, just I would like to understand how it works or search for a book through which to learn the base. I know there is a kind of secret from Atmel, so it's ok nvm I'll try to learn the base

 

clawson wrote:

awneil wrote:
replicate exactly how the stuff is implemented in actual AVR chips
As that is the intellectual property ("family jewels") on which a lot of the former Atmel empire was based I doubt anyone is going to supply too much detail about the exact working of AVRs internally.

 

Having said that a lot of these "chip tear down" sites analyse the polysilicon and aluminium pathways to reverse engineer how the chips work internally - so maybe that has been done for the AVR core somewhere?

 

But it's a fair bet that anything in the public domain in Verilog/VHDL purporting to be "AVR core" is almost certainly just a reimplemented, cycle accurate, "work alike" rather than anything based on the original AVR design.

I try to search for an open core

 

 

 

 

Perhaps you could recommend an good book about CPU principle?( better e-book)

I read many tutorials but everyone tell me the samething , <<CPU executes the istructions, ALU perform math>> I need to take a look "in the middle"

 

 

 

 

Last Edited: Fri. Apr 13, 2018 - 01:15 PM
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Cirano wrote:
Perhaps you could recommend an good book about CPU principle?

Try Search terms like "computer architecture", "CPU architecture", "ALU design", etc.

 

Wikipedia is always a good start ...

 

 

EDIT

 

CPU executes the istructions, ALU perform math

The ALU is a part of the CPU.

 

The clue is in the name: ALU = Arithmetic & Logic Unit

 

So, yes, "arithmetic" is basic "maths"

 

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Last Edited: Fri. Apr 13, 2018 - 01:23 PM
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Cirano wrote:
Perhaps you could recommend an good book about CPU principle?( better e-book)

Vax Architecture Reference Manual

 

https://www.amazon.com/Architect...

 

Jim

Click Link: Get Free Stock: Retire early!

share.robinhood.com/jamesc3274

 

 

 

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Funnily enough, I was just thinking that trying to find some old books would probably be a good idea - the basic principles remain the same, but there'd be a lot less modern complications!

 

So it maybe a good idea to get up and go to an actual library with actual books and look in the "computer science" section ...

 

 

EDIT

 

In this context, "old" would probably be about 1970s - 80s ...

 

surprise

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Last Edited: Fri. Apr 13, 2018 - 01:44 PM
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30 years ago, when my degree involved silicon fabrication and design THE seminal reference work was Mead and Conway. (*)
.
Of course back then you had to attend a university with clean room facilities if you wanted to be involved in chip design (personally I opted for software not hardware in the 3rd year so never got to play). But these days anyone with a CPLD or FPGA design kit can play the game. So if you are more interested in chip design than applying the ready made chips to system design I'd look at moving from micros to FPGAs.
.
A starting point is to get a logic simulator and build up your own CPU design in it. Hopefully Neil "barnacle" Barnes will be along shortly to remind us of the tool he used when designing his own CPU.
.
(*) the most expensive book I ever bought

 

EDIT2: back at my PC so I googled and found: https://www.amazon.co.uk/Introdu... - that's quite a bargain for a book that cost something like £50 in 1981 (probably the equivalent of something like £200 these days)

 

(and wow that was a good guess - I found an online calculator that tells me £50 in 1981 would be £204 now)

Last Edited: Fri. Apr 13, 2018 - 02:47 PM
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I’d suggest the basis for understanding processor design is the ‘finite state machine”. This is the basis for the CU (control unit) that pulls all the levers to make things happen. So to understand processor operation/design you need to fully understand the concept and implementation of a finite state machine.
As the others have mentioned, there’s a few secrets that are in the AVR that Atmel don’t quite explain. How the multiplier works is one, another is how it reads and writes the registers in one clock is another. One can only assume that they synthesize extra clocks or delays to make it happen. One thing to remember is everything in hardware takes a finite amount of time.

In terms of processor design and implementation, the 6502 has had an enormous amount of reverse engineering done on it. It might be worthwhile starting there and relating that knowlege back to the AVR. Other avenues might be looking at the design and implementation of old processors like the pdp8 and ibm1401.

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There is that guy who built a cpu from discrete transistors. In his page, he describes the architecture of his CPU in detail: http://www.megaprocessor.com/

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That was not the book I used ! but I don't know where my VLSI books are.(it was in 86-88)

For one project we used solo1000, (that was it was a university product later I have seen solo1400 for sale).

 

Back to the AVR

 

There are two different "main" version of the core.

The original version where I assume that the registers are placed on the memory bus.

And the xmega design (that newer tiny's also use), where they (I assume) are placed in the core logic (or an internal 2. bus). 

Benefit LD can be 1 clk, but the registers aren't memory mapped (some data sheets still seem to have cut and paste errors like they don't, and now it even seem that they try to hide memory mapping on the older chips!)

 

 

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Thanks Guys for your time,

I've been going through your link and suggestions and  by VLSI I have discovered a new world. ( and 6502  :]   http://6502.org/)

However before to goes so deep , I would like to ask the last question. If hope this question is not related to vlsi

 

Every istructions consist of one or more logic operation , so is the ALU responsible to execute always every IS ?

 

Control Unit

Apart from some special situations like a HALT instruction or the reset, the CPU constantly executes

program instructions. It is the task of the control unit

to determine which operation should be executed next and to configure the data path accordingly. To do so, another special register, the

program counter (PC), is used to store the address of the next program instruction. The control unit loads

this instruction into the instruction register (IR), decodes the instruction, and sets up the data path

to execute it. Data path configuration includes providing the appropriate inputs for the ALU (from

registers or memory), selecting the right ALU operation, and making sure that the result is written

to the correct destination (register or memory). The PC is either incremented to point to the next

instruction in the sequence, or is loaded with a new address in the case of a jump or subroutine call.

After a reset, the PC is typically initialized to $0000.

 

source : drawn from Vienna University of Technology

Introduction to Microcontrollers

Courses 182.064 & 182.074

 

When I read that article , I understand that ALU is the real executor and control unit chooses the right data to input to him.

 

Here my doubt:

source : drawn form  "Programming and Customizing the AVR Microcontroller" Dhananjay V. Gadre

 

He talk about ALU-related instruction . Does exist "ALU-not related" istruction ??

 

                               

 

 

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He talk about ALU-related instruction . Does exist "ALU-not related" istruction ??

Jumps, branches, calls, returns, loads, stores, moves, inputs, outputs, pushes, pops, shifts, rotates, bit operations, bit tests, etc.

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The clue is in the letter A. If its an "arithmetic" operation then the Arithmetic Logic Unit is involved but for other things like control flow, stack, etc it isn't.

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I am not convinced.  You might want to go and look at the data sheet for a "plain" ALU like the 74181 (?) - the operations typically include "none."

So I picture the AVR core as having the ALU with a couple of "source operand" buses, a "result destination", and an "operation code", all set up by the control unit.

An "ADD r3, r1" instruction causes the old contents of r1 and r3 to be placed on the source operand bus, sets up the ALU to do the add, and then stores the result in r3.

But the key thing to note with this theory is that a "MOV r3, r1" instruction STILL USES THE ALU.  It just sets the the "operation" to "source operand B, unchanged."  (give two bits A and B, "A" and "B" are both valid results of "logical operations.")  (or, sometimes, "mov" might be "add 0")

If this model holds true, them the multiplier is a separate bit of hardware that "taps" some of those buses, and "MUL r5,r6" causes the control logic to tell the multiplier to start multiply the values from the source operands, and then (on the second cycle?) works like an IN or LD instruction to R0/R1  (or maybe it gets the first half of the result in a the first cycle, and only needs the second cycle to store to the second register.)

 

This is all just guessing, of course.  But you see this happen on other CPU designs, where extra "functional units" (not the ALU itself) get tacked on in the various data paths, as long as the control logic can figure out somewhere to get bits to control it.   Multiply units, divide units, barrel shifters...  Not to mention designers getting creative with the instruction set ("increment is adding 0 with a carry-in!", or see the "constant generator" on MSP430.  Multiply&add instructions.   Or "we have XOR in the ALU, and a separate shifter, so we could combine them into a CRC-assist instruction!")  Getting carried away with this sort of thing in microcode (where you can more-or-less generate as many new control bits as you want) was one of the things that lead to RISC...

 

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We're quickly getting into the implementation details, of which Atmel don't really tell us much. Is the register bank one,two or three ported? As wetfw mentions, does a move go through the ALU? I was reading up on the RISC-V processor this morning and there is mention of it performing a move as an ADD Src,R0,Dest where R0 is a constant 0.

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Right.  The difference between most RISC processors (ARM 32bit, MIPS, PPC, and SPARC, anyway) and earlier machines is that the instruction usually contains the destination register separately, while on (AVR, 68k, x86, PDP11) the destination is always also one of the source registers.  Things like that cause lightbulbs to go off in my head: "aha; so THAT'S how this thing works."  (also, the time spent trying to write microcode for a bitslice.)

 

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Since MOVW only take 1 clk, it can't use the ALU !

So my guess is that also MOV have it's own logic.

 

But because the first AVR's didn't have MOVW, perhaps it's "hacked", and therefor I could easy be wrong.

 

 

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Maybe they added a 16 bit data path between the registers. Couldn't they have done the same to the program counter, so that ijmp would only take one cycle?

 

edit: I mean, ijmp is "movw PC, Z".

Last Edited: Sun. Apr 15, 2018 - 11:55 AM
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If the instruction before ijmp change Z you can't calc PC ahead.

 

But it could be done with rjmp because the new PC can be found in the prefetch:

 

perhaps take a look here :

 

ftp://imall.iteadstudio.com/Micr...

 

That is the clone that is out and that is more 16 bit than a "normal" AVR 

 

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Thanks , I 'm learning a lot from your answers and links

 

if you are courious, I share  last document ( i dont want stress you further  :]]]      ) , but it's about MIPS  (I looks like every instruction is ALU related , i.e. branch is a subtraction..)

 

http://homepage.divms.uiowa.edu/...

 

 

 

 

Last Edited: Sun. Apr 15, 2018 - 06:33 PM
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As evidenced by that document, there are a number of implementation decisions you can make.

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Just to make it clear, even if the AVR make one instruction pr clk, it will use both edges of the clk, so the internal logic actually the 2 "clocks". 

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But because the first AVR's didn't have MOVW

Interesting...never knew that....maybe they can add some more, like SUBW  & ADDW (specify two high bytes of two 2-byte pairs) like ADDW r27:r11 would execute r27:r26 + r11:r10--> r27:r26 

 

When in the dark remember-the future looks brighter than ever.

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No they ran out of instructions!

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Yup, the AVR opcode space is almost completely full. A way out would be using prefixes, but this would mean 2 word instructions, so they would be slower.

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avrcandies wrote:

...ADDW r27:r11 would execute r27:r26 + r11:r10--> r27:r26 

 

I don't do much assembly these days but surely that's just...

 

ADD R26, R10

ADC R27, R11

 

Most (all?) 16-bit instructions are 2 cycles so the above would take the same time.

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This is always worth a read...

 

http://ugweb.cs.ualberta.ca/~c27...

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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or have a mode where the H flag (rarely used )  in SFR is used as a 16 bit flag so 

 

ADD R26, R10

 

will behave as :

 

ADD R26, R10

ADC R27, R11

 

Or something like that

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What's to be gained though?

 

The ALU is, almost certainly, 8 bits wide. So you need to do two trips though it to do a 16-bit add or subtract. Which is 2 clocks cycles, the same as the two 8-bit adds. You'll also not want to do anything which causes the pipeline to stall as that will incur extra cycles.

 

If you really want a 16-bit ADD you could probably write a macro to do it and hide the underlying 8-bit operations.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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westfw wrote:

... the instruction usually contains the destination register separately, while on (AVR, 68k, x86, PDP11) the destination is always also one of the source registers.

 

To expand on that, there are, generally speaking, five different ways to design an instruction set based on each arithmetic instruction containing zero, one, two, three or four addresses. Consider an ADD instruction, you need to know four things...

 

1) Where operand 1 comes from

2) Where operand 2 comes from

3) Where to put the result

4) Where to get the next instruction from

 

As an exercise, pick a processor family and try to work out which type (0 to 4) it is.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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Why do I think of a stack machine when I read #50 ;)

 

1-3 given

4 inc PC

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