Atmega128 External RAM access question

Go To Last Post
9 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I ate too much at lunch and my brain is now low on oxygen.

Anyway, if I setup a Atmega128 to use external ram, do I really need to have all the address and data lines go to each respective line, such as A0 to A0, A1 to A1...D0 to D0 and so on.
Can't I run them like A0 to A11 ... D0 to D7 and so on to simplify a PCB layout.
Except for problems with testing as the old &H55 &HAA tests don't work like one would expect, I don't see any problems offhand.
Thanks,
Earl

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

When you turn on extmem, the rd and wr and ale pins start shaking. You at least need the 373 latch to catch the addr lo lines (if you need some addr lines like for dat/inst on an lcd for example). You can use a15 on pc7 for chip select if you only have one external device, so you dont need to run a14,a13,a12 to a 138 for a decoder, but that gives you 8 blocks of 4k to hook stuff up in. Using a15 for cs puts you external mem at 0x8000

Imagecraft compiler user

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I see no reason why this wouldn't work okay. As long as you can uniquely address the SRAM locations you're using, it should be functionally okay. The only thing I can think of where it might matter is that 1) it might initially seem confusing to anyone trying to troubleshoot the board and 2) If you are using canned libraries as part of automated testing, the address and data wouldn't be on the pins that the tester was expecting.

earlwb wrote:
Except for problems with testing as the old &H55 &HAA tests don't work like one would expect, I don't see any problems offhand.

Why wouldn't they work?

Dave

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I was just thinking about debugging, you are right they'd still work.
But someone that didn't know might be thrown off like ATE equip.

Thanks
I thought I had gone a bit buggy there after lunch.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Although i have never used it i think NAND memory has the equivalent of a 573 latch inbuilt so you just connet PORTA, PORTC and 3 lines of PORTG directly to the memory chip.

But as i havent used this type of memory, someone else we have to let you know if this is striclty true.

Lachlan

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Nand is an interesting animal. You basically need 13-14 pins to interface to nand flash. 8 data and 5-6 control. The control lines can be reduced a bit, with some external circuitry. Nand is also available in word wide modules, in which case you will need 16 address/data lines + 5-6 control lines.

Basically it's an 8 bit bus (or 16) that carries both data and address on it. And like SPI, you have a separate chip select for each chip. So you can hang additional NAND chips on the same bus, with only a penalty of 1 additional line per chip.

The actual protocol is pretty straight forward, and is also pretty standard across manufacturers and densities. You will likely spend more time working out the wear leveling algorithm to use than the actual interface code.

Atmels DataFlash is like A SPI version of the NAND flash, so if you're familiar with the dataflash, you'll be right at home with NAND.

To use NAND, you will need a good size ram buffer, big enough to hold the page size of the NAND you plan on using. There is no on-chip sram buffer, like there is in the DataFlash. This is one draw back for NAND with small micros. Expect that you will need 528 (512+16) bytes of buffer for any Nand from 8Mbit to 1GBit. Double that if using the word sized modules. Last time I looked, anything over 1GBit had a larger page size (2K+64/page).

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I can endorse that there is no reason to connect A0 to A0, D0 to D0 etc. I've seen some mixed up stuff done for exaclty that reason several times, to simplify PCB tracking. In fact I've written code for a commercially available 68K based board with failry scramble address lines. Bit of a pain to program EPROMs for it, as you have to write a scrambling tool.

Four legs good, two legs bad, three legs stable.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

John_A_Brown wrote:
I can endorse that there is no reason to connect A0 to A0, D0 to D0 etc. I've seen some mixed up stuff done for exaclty that reason several times, to simplify PCB tracking. In fact I've written code for a commercially available 68K based board with failry scramble address lines. Bit of a pain to program EPROMs for it, as you have to write a scrambling tool.

Unfortunately you cannot do that easily with NAND. Unless you remap all the commands, and addressing if the part does not consume all possible adresses in the size of the address transfer, which is always a multiple of 8 bits.

[edit]
I really should have gone and read the whole thread. I was responding to lachlans comments, which put me on the NAND flash track. I applogize for the confusion here.

For ordinary memory parts with separate address and data lines, you are free to connect them however you wish. It will be transparant to the micro.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

It won't make ANY difference if the DATA lines are scrambled.
HOWEVER if you scramble the address lines you might
(on some ram chips) effect the access times as the address lines
internally are set up for sequencial access. IE:
flipping the higher order lines changes 'pages'
while the lower lines remain within a page. Probably not
usually an issue. Also could effect EMI, and overall noise.