atmega128 clear bit on non-PWM compare match ?

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hello,

i don't see a simple thing in the data sheet from a atmega128.

 

when is the OCnA/OCnB/OCnC cleared ?

the table shows only when it is set.

 

thanks in advance.

 

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The bits you reference are under the control of the timer's compare unit. You can, I think, force them to particular states using the FOCn bits.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Sep 14, 2019 - 07:00 PM
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ok, but i mean,

 

Set OCnA/OCnB/OCnC on compare match
(set output to high level).

 

when it is cleared ?

 

 

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It is cleared when the counter resets/overflows to zero.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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The entries for 10 an 11 both say when the opposite polarity is actioned with the comment in parentheses

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alright, i'm gonna test this tomorrow.

it was for me a little bit confusing the way they write it down.

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No. The port bit is not cleared when the counter goes to zero. If you set a compare match to set the port bit, when the counter gets to the compare value, the port bit is set. If you do nothing, the port bit remains set. What you. might do is also interrupt on the compare match and the isr code sets the timer to clear the port bit at x time.

You have three choices:
1. Disconnect the port pin from the compare function and control the port pin as you normally would.
2. Use the force feature to set/clear the port pin
3. Set up another compare to manipulate the port pin as you wish.

Last Edited: Sun. Sep 15, 2019 - 03:29 AM
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actually i want to make a puls train to steer a stepper motor with acc. & dec.

am i on the correct way to do that ? ore can i better take a other mode from timer1. 

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Surely you choose the most appropriate WGM mode.

And use an ISR() to select the next pulse width, mode etc.

 

Life is much easier if you just draw a typical pulsetrain and indicate any timing constraints.

Especially other interrupts.

 

If your pulses are relatively slow you don't need to worry about nanosecond perfect timing.

You can probably accept interrupt latency of several microseconds.

 

David.

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i just did a small test witch is not working the way i expected. in the simulator it looks OK , but on the hardware its not running correct.

 

i'm gonna post tomorrow a simple code, its working whit the acc. in steps, 10 steps from 0 rpm to 24 rpm.

thanks for now.

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it takes a little bit longer, have to make long days for my work.

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Kartman wrote:
2. Use the force feature to set/clear the port pin

 

do someone now how i can do that ?

thnx

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Download datasheet and search for ‘force’

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i already did, but i still can't find it.

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Open PDF.   Search for "force" e.g. with ctl-F or F3.

 

Life is easier if you search for "whole word"

 

I presume that you have the "full" datasheet.    My PDF is 389 pages dated 2004.    Modern datasheets will be a similar size.

 

The "short" (Summary) datasheets are completely useless.

 

David.

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i have the full datasheet (400 pages).

 

is see how i can force  OC1A (pin b5) to a logical 1 with the FOC1A

but how can i forced to a logical 0 ?

 

now i make a pulse train for my stepper with the "toggle on compare match" option.

but that is not easy to calculate with. (toggle with 1ms will give a cycle of 2 ms).

 

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Post a typical sequence.

 

Then someone might help you achieve it.

 

David.

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yes i'm working on it wright now smiley

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trixo wrote:

is see how i can force  OC1A (pin b5) to a logical 1 with the FOC1A

but how can i forced to a logical 0 ?

What does the datasheet say will happen when you set that bit?

• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting.
Note that the FOCnA/FOCnB/FOCnC bits are imple-mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.

Table 58. Compare Output Mode, non-PWM
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1 Toggle OCnA/OCnB/OCnC on compare
match.
1 0 Clear OCnA/OCnB/OCnC on compare
match (set output to low level).

1 1 Set OCnA/OCnB/OCnC on compare match
(set output to high level).

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Fri. Sep 27, 2019 - 01:12 PM
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yes i saw that (of course wink) i think i have interpreted it in the wrong way. i'm gonna checked.

theusch thanks for your help yes.

 
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i picked this tread up again, 

 

when a compare mach appears, and the (table 58) is  1 1 Set OCnA/OCnB/OCnC on compare match( set output to high level).

the OC1A pin is set to "1"

 

now we gonna force a compare: wright "1" to FOC1A datasheets says: The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.

but that is "1" nothing changed ???

 

what do i not see (en understand) ?

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COMnx bits determine if the pin will go hi,low, toggle or nothing when there is a compare match or force compare.

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yes thats clearly, but how its becomes low once it is set ?

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Set the COMnx bits for port low and do a compare or force compare.

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that sounds logical, thanks for the tip. one of these days i'm gonna checked it.

yes