ATMega External Clock

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A few observations.

On the title page of ATMega8 datasheet everybody can read "Fully Static Operation" typed by bold font among features of the device.

On the p. 30 of the same document everybody can read another text typed by an ordinal font:

"When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behaviour. It is required to ensure that the MCU is kept in Reset during such changes in the clock
frequency."

Is there anybody who can explain me how the statemens can agree? For me the statement on the title page seems to be false advertising.

And another observation. Early ATMega128 datasheets has no such restriction but the last I have downloaded today has it. Anybody knows why the restriction was added?

Another question. Why nearly all ATMega datasheets on http://www.atmel.com/atmel/produ... are Preliminary for a few years (even "Not Recommended for New Designs")?

Is Atmel a stable company now?

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Yes,
here is really strange "Fully Static Operation"
and this 2% ...
Maybe somebody or Atmel can explain,
which kind of "behaviour" here can be ?

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Hi (i'm not from Atmel, but anyway..),

To me anyway "fully static operation" means that the chip can run off ANY clock frequency, even like 0.1 Hz, as the design of the chip doesn't have any minimum timing requirements. Checking the "external drive requirements" show that thier is NO maximum clock period either, so you can basically run it off any (stable) frequency.

Chances are that during testing they found if you changed the clock frequency very suddenly it might make the micro go crazy. All they are doing is telling you the results of the testing.

If you go to page 267, it says that they added that in revision 2486E-06/02 (I assume the 06/02 means 2002, 6th month).

I think almost every data sheet does this, lists features that are only applicable under certain operating conditions.

The reason the data-sheet is still lised as "Preliminary" is that they haven't got around to testing everything. Some parts of the data-sheet are marked TBD (To Be Determined). But the chips have been out for a while...

The AtMegas that are "not reccommened for new designs" are old, and they have since made a (better) replacement for it. Atmel is just warning you that you shouldn't use this for a new design as you will have trouble getting them.

https://www.avrfreaks.net/Devices... is a good source for info on what teh status of certain chips are.

I'm not an investor or from Atmel or anything, but I would venture to say that Atmel is indeed a stable company. Thier AVR processors are reaching huge popularity, and they are releasing new processors and development kits (AtMega169 and STK502), and thats just thier AVR division!

-Colin

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Yes, I use AVRs intensively too thinking that them have a good convenient architecture and some superior featuires. So I'm very interesting in the stability of Atmel. The current situation with permanently "Preliminary" datasheets and some other symptoms make me nervous. It seems that AVR chips developers are losing control other their projects or are too busy. Just symptoms. But such symptoms were observed with a lot of companies before selling of them.

Unfortunately the added in the ATMega datasheets requirement is very strange and it breaks my current project. I think too that it is a bug found while testing or by consumers but I can't be satisfied by brevity of it's description. What does the phrase "can lead to unpredictable behaviour" mean? Don't the developers know what the behaviour can be?

Another bad symptom I have found just now - Atmel's price on Nasdaq... Visit http://www.nasdaq.com and see price charts for Atmel for a last year or two. In October it was close to bankraptcy. Very bad. I'm not an investor but I will loss a lot in the case of Atmel's bankruptcy...

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Hello,

Try e-mailing atmel's tech support avr@atmel.com, they might be able to help you more.

In your current project, does the clock change constantly, or is it just once and a while it will have to change more than 2%?

The only real way to avoid the reliance on Atmel (or any one company) is to use a multi-sourced processor, like the 8051 that many many manufactures make.

BTW I looked up Microchip on the stock charts as well, and around the same time it had a huge spike downward. Microchip's stock price is higher though to start with.. but it might have been an industry thing around that time, not just Atmel.

-Colin

PS: Maybe Atmel should have used bigger decoupling caps on its stock :p

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I don't use PICs. :)

In my project the clock changes sometimes... I use ATMega with PDIUSBD12 in bus-powered mode. The ATMega is to program clock frequency during start-up. And during USB suspend the D12 changes clock frequency to 32 KHz. Very common project as PDIUSBD12 is a popular USB function chip. And according to datasheet ATMega128 can't work with it!
I think it will not be too serious if the system will hang very rarely during USB bus suspend (of course I'd like to avoid this) but I'd like to understand possibilities clearly. And I have to protect EEPROM and flash from corruption...

Eugene.

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When looking over the datasheet for the new Mega169, I was impressed with the variety of power-saving modes available. In particular, the CLKPR system clock prescale register can specify a change in the system clock prescaler from /1 to /256 on the fly. Perhaps you could use this device, and sense when the lower speed is needed and change the prescaler. I don't know any other AVRs that have this feature.

Lee

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Hi,

The mega169 looks really nice.. no stock at digikey yet though...

In your application it might not be so bad. When the USB bus goes into suspend do you even need the processor, like could you just hold it in reset when the USB bus goes into suspend?

I would disable the ability to use the SPM instruction at least in application memory section. Could you use a watchdog timer? I guess it depends on your application, but I mean if you can just get the chip to reset (or be held in reset when the clock changes) it shouldn't be too bad.

It seems to me like certain chip functions only are affected by this change in clock speed. What ones I don't know, but it does seem like an odd requirement. I would check with Atmel to see what they tell you.

-Colin

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Lee:

"the CLKPR system clock prescale register can specify a change in the system clock prescaler from /1 to /256 on the fly... I don't know any other AVRs that have this feature."

The Mega128 has a similar ability via the XDIV register, though the maximum prescale is only /129 (but with finer control over exactly what value you use).

Regards
Chris