ATmega edge detector characteristics?

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Hello,

As I couldn't find in the datasheets this info, would anyone of you know the edge detector characteristics of a T0 / T1 input pin on a ATmega device being powered on 5V? Does it have a hysteresis cycle? Is it subject to noise?

My electronic projects blog >> www.limpkin.fr

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No hysteresis is mentioned, anywhere. I don't know of any AVR input with hysteresis.

I would expect it to respond to noise that satisfies minimum pulse width requirements.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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and what would be this minimum pulse requirement?

My electronic projects blog >> www.limpkin.fr

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I believe the edge must last a minimum of 1 system clock pulse. I know that I have seen that in the datasheet for edge detection of external interrupts, but I think that it applies to all edge detectors in the AVR.

Regards,
Steve A.

The Board helps those that help themselves.

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ka7ehk wrote:
I don't know of any AVR input with hysteresis.
Since we don't have any specific AVR ATmega processor chip in this thread, check your data sheet for "Pin Thresholds and Hysteresis" or just search the PDF for "Hysteresis". The TWI has a specification for "Hysteresis of Schmitt Trigger Inputs". All of the input pins are covered by the "Pin Thresholds and Hysteresis" specification.

I found the above in the AT90CAN family data sheet.

Koshchi wrote:
I believe the edge must last a minimum of 1 system clock pulse.
That would be a really slow edge transition :). Isn't it the duration of the sustained signal voltage after the edge transition? The data sheet I/O Ports section usually has information on the .5 to 1.5 AVR clock cycle input pin synchronization. However, the timer/counter Tn input pin has a longer delay than other input pins of 2.5 to 3.5 AVR clock cycles. The data sheet timer/counter prescaler section usually has this information.

Last Edited: Wed. Mar 17, 2010 - 05:33 PM
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Sorry for not mentionning it, i'm using a ATMega644 :)

My electronic projects blog >> www.limpkin.fr

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OK, learned something new!

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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limpkin wrote:
i'm using a ATMega644 :)
Then you would lookup section 27.9 Pin Threshold and Hysteresis.

The T0 / T1 input pin synchronization isn't mentioned in this data sheet, but I would expect it to be the same as other ATmegas. So, your edge detection at the timer/counter input could have a 1 AVR clock cycle input pin synchronization induced jitter. This is one reason why the maximum frequency of an external timer/counter clock source must be less than fclk_I/O / 2.5.

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27.9 section???? my datasheet stops at 27.8!
Thanks for the info!

My electronic projects blog >> www.limpkin.fr

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Quote:

This is one reason why the maximum frequency of an external timer/counter clock source must be less than fclk_I/O / 2.5.

When researching this, I tried to find that bit of info in the datasheet as it has been "tribal knowledge". Did you find it somewhere? (in any model? what section?)

IIRC you need near-50%-duty when you approach whoopee speeds; each half of the cycle must be 1+ AVR clocks, right?

You can put lipstick on a pig, but it is still a pig.

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I used the ATmega644 data sheet 2593M–AVR–08/07 to find section 27.9 Pin Threshold and Hysteresis. Maybe your data sheet is really old?

In the ATmega164P/324P/644P version 8011N-AVR-01/10 data sheet it is section 26.1.9 "Pin Threshold and Hysteresis". This one is also missing the timer/counter prescaler information.

The timer/counter external clock source tolerance fclk_I/O / 2.5 recommendation is located in the AT90CAN32/64/128 version 7679H-CAN-08/08 data sheet section 11.1.3 External Clock Source. Also the ATmega640/1280/1281/2560/2561 version 2549L-AVR-08/07 data sheet section 18.3 External Clock Source. The ATmega128A data sheet section 16.3 External Clock Source. Probably any ATmega data sheet that doesn't forget to include the timer/counter prescaler section for the synchronous operation only timer/counters.

It appears ATMEL is being conservative on this maximum frequency recommendation. Applying pure Nyquist to a one AVR clock cycle detection uncertainty makes an exact divide by 2 a sampling failure frequency. It obviously does need some extra breathing room and the smarter people than me at ATMEL came up with divide by 2.5 as a safety margin.

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Aah, yes--right where I was looking. :) (I was searching for the terms used in the diagrams, which aren't the same as in that text.)

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.