Atmega 328p failing to verify using ICE and AS 7

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I've been trying to program an atmega 328p on a PCB that I designed using the ICE over ISP. It uses a 8mHz external clock, see below:

I've selected an 8mHZ external clock in the fuse bits, and change the ISP frequency accordingly (2MHz). At first I had left most of the other bits (except the clock div enable) the same as their default values.

 

When I try to program it, I get the following error:

 

I've googled that error, and the similar ones I've been getting, and I haven't come up with much. According to my research, possible sources include:

1) The reset pin; mine is pulled high and the oscilloscope confirms that

2) The fuse bits; I think mine are OK, but then again it doesn't work (see image below)

3) Connection issues; my connector appears to have the correct interface and I have no problems programming the fuse bits. I can make changes and they take hold

4) Clock problems: I see a clean 3.3 V 8MHz clock when I output it to PORTB0

5) Programming frequency for ISP: In AS it says 1/4 of your clock, so 2MHz in my case

 

If anyone has an idea, it would be greatly appreciated!

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Last Edited: Wed. Aug 8, 2018 - 04:55 PM
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Flabelle wrote:
and change the ISP frequency accordingly (2MHz)

In AS it says 1/4 of your clock, so 2MHz in my case

It doesn't HAVE to be 1/4, it just can't be any MORE than 1/4. In fact at 2MHz for an 8MHz clock you are right at the limit and if you actually got something wrong in your previous fuse setting then you are now well over. I'd put it back to 250kHz or less and see if you can then contact. If so you likely failed to enable the 8MHz source. Having said that I do note:

Flabelle wrote:
4) Clock problems: I see a clean 3.3 V 8MHz clock when I output it to PORTB0

so maybe that's not the case and you have achieved 8MHz? Even so I'd still try winding the ISP speed down a bit.

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clawson wrote:

 

It doesn't HAVE to be 1/4, it just can't be any MORE than 1/4. In fact at 2MHz for an 8MHz clock you are right at the limit and if you actually got something wrong in your previous fuse setting then you are now well over. I'd put it back to 250kHz or less and see if you can then contact. If so you likely failed to enable the 8MHz source. Having said that I do note:

 

Haha, that'll teach me to read a little more carefully.. The ISP speed was indeed part of the problem. 

 

Is it possible that because the clock is slightly slower than 8MHz (After closer examination, it looks to be ~7.9-7.95 MHz) 2MHz for the ISP clock was too fast?

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Why did you tie the AREF pin to VCC?  Normally it just has 100nf cap to gnd.

 

Jim

 

Click Link: Get Free Stock: Retire early!

share.robinhood.com/jamesc3274

 

 

 

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ki0bk wrote:

Why did you tie the AREF pin to VCC?  Normally it just has 100nf cap to gnd.

 

Jim

 

 

I'm not using the ADC, so I just tied AREF high and left it alone. Is that a bad thing?

 

Edit: I have no justification for that design choice, its just the first thing that came to mind.

Last Edited: Wed. Aug 8, 2018 - 07:18 PM
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Flabelle wrote:
Is that a bad thing?

Best to let float or do as DS & App Notes says and attach a cap to bypass filter internal vref.

 

Jim

 

Click Link: Get Free Stock: Retire early!

share.robinhood.com/jamesc3274

 

 

 

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Ok, in that case I'll cut that trace and fix it in the schematic.

 

Thanks for finding that mistake!